公开(公告)号：US20240213185A1

公开(公告)日：2024-06-27

申请号：US18146886

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Manicon Murugan ,  Sylvester Ankamah-Kusi

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01P3/00 ,  H01P3/12 ,  H01P5/107 ,  H01P11/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01P3/003 ,  H01P3/121 ,  H01P5/107 ,  H01P11/002 ,  H01P11/003 ,  H01L2223/6633

Abstract: An electronic device includes a multilevel package substrate with a horizontal substrate integrated waveguide (SIW) with a channel, a vertical SIW with an opening, a grounded coplanar waveguide (GCPW), a first transition between the horizontal SIW and the GCPW, and a second transition between the horizontal and vertical SIWs, as well as a semiconductor die having conductive structures coupled to a signal trace and a ground trace of the GCPW, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US20240113413A1

公开(公告)日：2024-04-04

申请号：US18530179

申请日：2023-12-05

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/66 ,  H05K1/02

CPC classification number: H01Q1/2283 ,  H01L23/3114 ,  H01L23/66 ,  H05K1/0237 ,  H01L2223/6677

Abstract: A described example includes an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

公开(公告)号：US11784114B2

公开(公告)日：2023-10-10

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Makarand Ramkrishna Kulkarni ,  Osvaldo Jorge Lopez ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16238

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20230317673A1

公开(公告)日：2023-10-05

申请号：US17710941

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Vivek Swaminathan Sridharan ,  Rajen Manicon Murugan ,  Patrick Francis Thompson

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L24/24 ,  H01L24/16 ,  H01L24/20 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/73209 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2924/37001 ,  H01L2924/186 ,  H01L2924/182 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/17134

Abstract: A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.

公开(公告)号：US20230090365A1

公开(公告)日：2023-03-23

申请号：US17689153

申请日：2022-03-08

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01Q3/44 ,  H01Q1/38 ,  H01Q9/04

Abstract: An electronic device includes a die, a packages structure, and a multilevel redistribution structure having a first via, a first level, a second via, a second level, and passivation material. The first level has a conductive antenna, the first via extends between the conductive antenna and a conductive terminal of the die, and the passivation material extends between the first and second levels. The second via extends through the passivation material between the first and second levels. The second level has a conductive reflector.

公开(公告)号：US11600932B2

公开(公告)日：2023-03-07

申请号：US17232849

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01Q23/00 ,  H01L23/66

Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including ≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

公开(公告)号：US11600581B2

公开(公告)日：2023-03-07

申请号：US17231897

申请日：2021-04-15

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Hassan Omar Ali ,  Baher Haroun ,  Yigi Tang ,  Rajen Manicon Murugan

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/495

Abstract: A packaged electronic device includes a multilayer lead frame having first and second trace levels, a via level therebetween, a conductive feed structure, and a conductive reflector wall. The first trace level includes a conductive coupler antenna and a conductive ground structure that extends in a plane of orthogonal first and second directions, and a portion of the conductive coupler antenna faces outward along a third direction orthogonal to the first and second directions. The conductive reflector wall has an opening and extends along the third direction between the first and second trace levels around a portion of the conductive coupler antenna. The conductive feed structure is coupled to the conductive coupler antenna and extends along the first direction through the opening of the conductive reflector wall.

公开(公告)号：US20230063343A1

公开(公告)日：2023-03-02

申请号：US17410535

申请日：2021-08-24

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang ,  Jonathan Almeria Noquil ,  Makarand Ramkrishna Kulkarni

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L21/60

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas and the second level having a second side with conductive landing pads. The electronic device includes a die with conductive terminals electrically coupled to respective ones of the landing areas, as well as solder balls attached to respective ones of the landing pads, and a package structure that encloses the die and a portion of the multilevel package substrate.

公开(公告)号：US20230044284A1

公开(公告)日：2023-02-09

申请号：US17747740

申请日：2022-05-18

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

公开(公告)号：US20220336383A1

公开(公告)日：2022-10-20

申请号：US17231897

申请日：2021-04-15

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Hassan Omar Ali ,  Baher Haroun ,  Yigi Tang ,  Rajen Manicon Murugan

IPC: H01L23/66 ,  H01L23/495 ,  H01L21/48

Abstract: A packaged electronic device includes a multilayer lead frame having first and second trace levels, a via level therebetween, a conductive feed structure, and a conductive reflector wall. The first trace level includes a conductive coupler antenna and a conductive ground structure that extends in a plane of orthogonal first and second directions, and a portion of the conductive coupler antenna faces outward along a third direction orthogonal to the first and second directions. The conductive reflector wall has an opening and extends along the third direction between the first and second trace levels around a portion of the conductive coupler antenna. The conductive feed structure is coupled to the conductive coupler antenna and extends along the first direction through the opening of the conductive reflector wall.