公开(公告)号：US20160329423A1

公开(公告)日：2016-11-10

申请号：US15049209

申请日：2016-02-22

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract translation: 半导体器件包含垂直MOS晶体管，其沟槽中的沟槽栅极延伸穿过垂直漂移区到漏极区。 这些沟槽在门下有现场板; 场板与漂移区相邻并且具有多个段。 将场板与漂移区分离的沟槽中的电介质衬垫的厚度大于门和主体之间的栅极电介质层。 电介质衬垫在沟槽底部的场板的下段上比在栅极正下方的上段更厚。 沟槽栅极可以与场板电隔离，或者可以连接到上部段。 场板的段可以彼此电隔离或者可以在沟槽中彼此连接。

公开(公告)号：US09299830B1

公开(公告)日：2016-03-29

申请号：US14706927

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract translation: 半导体器件包含垂直MOS晶体管，其沟槽中的沟槽栅极延伸穿过垂直漂移区到漏极区。 这些沟槽在门下有现场板; 场板与漂移区相邻并且具有多个段。 将场板与漂移区分离的沟槽中的电介质衬垫的厚度大于门和主体之间的栅极电介质层。 电介质衬垫在沟槽底部的场板的下段上比在栅极正下方的上段更厚。 沟槽栅极可以与场板电隔离，或者可以连接到上部段。 场板的段可以彼此电隔离或者可以在沟槽中彼此连接。

公开(公告)号：US09117687B2

公开(公告)日：2015-08-25

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/761 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract translation: 包含在低电压范围内工作的第一多个MOS晶体管的集成电路和在中间电压范围内工作的第二多个MOS晶体管也可以包括高电压MOS晶体管，其操作在明显高于 低电压和中等电压范围，例如20至30伏特。 高压MOS晶体管具有闭环配置，其中漏极区域被栅极包围，栅极又被源极区域包围，使得栅极不与场氧化物重叠。 集成电路可以包括高压MOS晶体管的n沟道版本和/或高压MOS晶体管的p沟道版本。 n沟道版本和p沟道版本的注入区域与第一和第二多个MOS晶体管中的注入区域同时形成。

公开(公告)号：US20240113217A1

公开(公告)日：2024-04-04

申请号：US17958205

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Thomas Grebs ,  Yunlong Liu ,  Sunglyong Kim ,  Lindong Li ,  Peng Li ,  Seetharaman Sridhar ,  Yeguang Zhang ,  Sheng pin Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/823437 ,  H01L27/092 ,  H01L29/42368

Abstract: An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.

公开(公告)号：US11764208B2

公开(公告)日：2023-09-19

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L29/40

CPC classification number: H01L27/0259 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7818 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/732

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11658241B2

公开(公告)日：2023-05-23

申请号：US16237210

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Thomas Eugene Grebs

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/872 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/872

Abstract: An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

公开(公告)号：US20230132375A9

公开(公告)日：2023-04-27

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11127852B2

公开(公告)日：2021-09-21

申请号：US16233643

申请日：2018-12-27

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Yunlong Liu ,  Fei Ma

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates.

公开(公告)号：US10714474B2

公开(公告)日：2020-07-14

申请号：US15636055

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/761 ,  H01L29/06 ,  H01L27/088 ,  H01L29/49

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US10672901B2

公开(公告)日：2020-06-02

申请号：US16277719

申请日：2019-02-15

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Satoshi Suzuki ,  Simon John Molloy

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.