公开(公告)号：US20170019067A1

公开(公告)日：2017-01-19

申请号：US14930210

申请日：2015-11-02

Applicant: Texas Instruments Incorporated

Inventor： Sudipto Chakraborty

IPC: H03D7/14 ,  H03K5/01 ,  H03H11/20

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03H11/20 ,  H03K5/01 ,  H03K2005/00286

Abstract: An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals. The gain signals may be DC or AC, which allows configuration of the circuit as a phase shifter or an upconversion mixer, and the load may be presented by a transform in which the phase also depends on the relative coupling from the in-phase and quadrature-phase sides of the phase interpolator.

Abstract translation: 一种用于在所选相位产生周期性信号的模拟电路，包括接收正交差分RF信号的一个或多个相位内插器和一对差分增益信号。 差分同相RF信号被施加在尾部晶体管的相应栅极处，并且第一差分增益信号施加在耦合到每个尾部晶体管的晶体管对的栅极之间。 正交相位RF信号和第二差分增益信号类似地应用于晶体管（即，一对晶体管对）和相关联的尾部晶体管的另一个四边形。 连接到每对中的一个晶体管的负载以对应于第一和第二增益信号的比率的相位接收输出信号。 增益信号可以是DC或AC，其允许将电路配置为移相器或上变频混频器，并且可以通过变换来呈现负载，其中相位还取决于来自同相和正交的相对耦合 相位插值器的相位侧。

公开(公告)号：US20170005616A1

公开(公告)日：2017-01-05

申请号：US14755462

申请日：2015-06-30

Applicant: Texas Instruments Incorporated

Inventor： Sudipto Chakraborty

IPC: H03B5/12

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03F3/211 ,  H03F3/213 ,  H03F3/245 ,  H03G1/0005 ,  H03G3/3042 ,  H04B2001/0416

Abstract: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

Abstract translation: 可变增益功率放大技术包括利用包括在振荡器中的一个或多个无功分量的网络产生第一振荡信号，以及经由包括在无功分量的网络中的一个或多个抽头输出第二振荡信号 。 第二振荡信号具有与第一振荡信号成比例且小于第一振荡信号的幅度。 功率放大技术还包括选择用于产生功率放大输出信号的第一和第二振荡信号之一，以及放大所选择的第一和第二振荡信号中的一个以产生功率放大输出信号。

公开(公告)号：US09520861B1

公开(公告)日：2016-12-13

申请号：US14971465

申请日：2015-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael A. Wu ,  Sudipto Chakraborty

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A system to generate an oscillator signal. The system includes a multi-stage oscillator, where each stage generates an output. The system also includes a first weighting circuit coupled to the multi-stage oscillator. The first weighting circuit taps the outputs of at least some of the stages and applies a first variable weighting factor to each output of the tapped stages to generate a first weighted output for each of the tapped stages. The system also includes a first summing circuit coupled to the first weighting circuit. The first summing circuit sums the first weighted outputs of the tapped stages to produce the oscillator signal.

Abstract translation: 用于产生振荡器信号的系统。 该系统包括多级振荡器，其中每个级产生输出。 该系统还包括耦合到多级振荡器的第一加权电路。 第一加权电路抽取至少一些级的输出，并且将第一可变加权因子应用于抽头级的每个输出，以产生每个抽头级的第一加权输出。 该系统还包括耦合到第一加权电路的第一求和电路。 第一求和电路将抽头级的第一加权输出相加以产生振荡器信号。

公开(公告)号：US20160142059A1

公开(公告)日：2016-05-19

申请号：US14541578

申请日：2014-11-14

Applicant: Texas Instruments Incorporated

Inventor： Sudipto Chakraborty

IPC: H03K23/70

CPC classification number: H03K23/70 ,  H03K3/012

Abstract: A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.

Abstract translation: 差分奇整数分频器提供具有自对准50％占空比的施加的正方形或正弦时钟信号的低功耗和紧凑的次谐波。 奇整数分频器电路包括以环形方式连接的一组低功率延迟单元。 每个延迟单元包括连接到MOS晶体管的栅极的两个差分双端口输入。 例如，这些奇数整数除数器包括一系列低功率锁存电路，其定制配置为最小净空和低功耗。 然后可以将这些输出相量与适当的权重因子组合，以从输入的方波形中提供近似正弦波形。 使用组合逻辑电路可以缩短或拉伸本征的50％占空比。

公开(公告)号：US20160036382A1

公开(公告)日：2016-02-04

申请号：US14447478

申请日：2014-07-30

Applicant: Texas Instruments Incorporated

Inventor： Sudipto Chakraborty

IPC: H03B5/12

CPC classification number: H03B5/1215 ,  H03B1/00 ,  H03B5/08 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/125 ,  H03B5/1262 ,  H03B5/1296 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: A wide tuning range oscillator system uses multiple active cores with cross-coupled transistors and multiple tapped inductors having windings that can be connected to circuit nodes. These active cores are connected to a pair of symmetric tapping points and are switched ON/OFF by biasing elements. Biasing schemes and the topology of the individual cross-coupled cores may be different from each other. The tapping points are symmetrically arranged around the center point of the inductor. One or more of the active cores may be enabled for tuning the center frequency of the oscillator system.

Abstract translation: 宽调谐范围振荡器系统使用具有交叉耦合晶体管的多个有源核心和具有可以连接到电路节点的绕组的多个抽头电感器。 这些活性芯连接到一对对称的攻丝点，并通过偏置元件接通/断开。 各个交叉耦合核心的偏置方案和拓扑可能彼此不同。 攻丝点围绕电感器的中心点对称排列。 可以使能一个或多个有源内核来调谐振荡器系统的中心频率。

公开(公告)号：US20150381191A1

公开(公告)日：2015-12-31

申请号：US14318228

申请日：2014-06-27

Applicant: Texas Instruments Incorporated

Inventor： Michael A. Wu ,  Sudipto Chakraborty

IPC: H03L7/099 ,  H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/0996 ,  H03L7/16

Abstract: A circuit includes a ring oscillator component and a phase selecting component. The ring oscillator component outputs a clock signal having a clock frequency, fCLK, and has a number n of delay components connected in series. The phase selecting component outputs a feedback clock signal, and has a switching component. The switching component can be in a first state and a second state, and can switch from the first state to the second state. The switching component outputs, in the first state, an output of a first delay component such that a signal output from the first delay component is the feedback clock signal having a first phase. The switching component outputs, in the second state, an output of a second delay component such that a signal output from the second delay component is the feedback clock signal having a second phase.

Abstract translation: 电路包括环形振荡器部件和相位选择部件。 环形振荡器组件输出具有时钟频率fCLK的时钟信号，并且具有串联连接的数量n个延迟分量。 相位选择分量输出反馈时钟信号，具有开关元件。 切换部件可以处于第一状态和第二状态，并且可以从第一状态切换到第二状态。 开关部件在第一状态下输出第一延迟部件的输出，使得从第一延迟部件输出的信号是具有第一相位的反馈时钟信号。 切换部件在第二状态下输出第二延迟分量的输出，使得从第二延迟分量输出的信号是具有第二相位的反馈时钟信号。

公开(公告)号：US20150349839A1

公开(公告)日：2015-12-03

申请号：US14825714

申请日：2015-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

IPC: H04B1/7176

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

Abstract translation: 本文公开了适用于体区网络的符号调制系统。 符号调制系统包括符号映射器。 符号映射器被配置为确定符号的传输代表将发生的预定符号传输间隔内的时间。 该时间基于符号的值和跳时序列的值来确定。 该时间是从基于多个符号值的时隙中选出的，以及在每个基于符号值的时隙内的多个跳时序列子时隙。 符号映射器被配置为在符号传输间隔内产生单个保护间隔。 单个保护间隔定位成终止符号传输间隔。

公开(公告)号：US09130636B2

公开(公告)日：2015-09-08

申请号：US13798675

申请日：2013-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudipto Chakraborty ,  David Le Deaut ,  Josef Einzinger ,  Jens Graul

IPC: H04B1/38 ,  H04B1/10 ,  H04B1/04

CPC classification number: H03G3/3042 ,  H03F1/02 ,  H03F3/24 ,  H04B1/04 ,  H04B1/0458 ,  H04B1/10 ,  H04B1/44 ,  H04B2001/0408 ,  H04B2001/045

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract translation: 收音机包括发射和接收RF信号的收音机。 收发器包括发射器，变压器和接收器，变压器耦合到发射机和接收机之间并共享。 谐振器由发射器和接收器的变压器和电容元件的组合形成。

公开(公告)号：US20150177326A1

公开(公告)日：2015-06-25

申请号：US14137994

申请日：2013-12-20

Applicant: Texas Instruments Deutschland GMBH ,  Texas Instruments Incorporated

Inventor： Sudipto Chakraborty ,  Jens Graul

IPC: G01R31/317 ,  H04B17/00

CPC classification number: G01R31/31716 ,  G01R31/2822 ,  G01R31/3187 ,  H04B17/13 ,  H04B17/19

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.

Abstract translation: 芯片上的系统（SoC）包括收发器，包括具有功率放大器的发射机和具有信号缓冲器的接收机。 发射器和接收器中的至少一个具有可配置部分，其可被配置为产生波形范围（波形以及占空比）。 内置自检（BIST）逻辑的低成本耦合到收发器。 BIST逻辑可操作地校准收发器的可配置部分以产生具有小于阈值的幅度的选定谐波分量的波形。 可以通过选择具有低谐波分量的优化波形来动态地减少收发器消耗的电流。

公开(公告)号：US20140233609A1

公开(公告)日：2014-08-21

申请号：US14264708

申请日：2014-04-29

Applicant: Texas Instruments Incorporated

Inventor： June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

IPC: H04B1/7176

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

Abstract translation: 本文公开了适用于体区网络的符号调制系统。 符号调制系统包括符号映射器。 符号映射器被配置为确定符号的传输代表将发生的预定符号传输间隔内的时间。 该时间基于符号的值和跳时序列的值来确定。 该时间是从基于多个符号值的时隙中选出的，以及在每个基于符号值的时隙内的多个跳时序列子时隙。 符号映射器被配置为在符号传输间隔内产生单个保护间隔。 单个保护间隔定位成终止符号传输间隔。