公开(公告)号：US20230377624A1

公开(公告)日：2023-11-23

申请号：US18362685

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

CPC classification number: G11C8/14 ,  H01L21/8221 ,  H10B51/20 ,  H10B99/00

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US11776602B2

公开(公告)日：2023-10-03

申请号：US17814341

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

CPC classification number: G11C8/14 ,  H01L21/8221 ,  H10B51/20 ,  H10B99/00

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US20230165011A1

公开(公告)日：2023-05-25

申请号：US18151682

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

公开(公告)号：US11552103B2

公开(公告)日：2023-01-10

申请号：US17018139

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/11597 ,  G11C7/18 ,  G11C11/14 ,  H01L27/11587

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

公开(公告)号：US11545500B2

公开(公告)日：2023-01-03

申请号：US17157489

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  G11C7/18

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

公开(公告)号：US11532640B2

公开(公告)日：2022-12-20

申请号：US17012848

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  G11C11/56 ,  H01L27/11587 ,  G11C11/22 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20220367518A1

公开(公告)日：2022-11-17

申请号：US17874908

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US20220359270A1

公开(公告)日：2022-11-10

申请号：US17814626

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H01L27/11597 ,  H01L21/8239

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US20210407848A1

公开(公告)日：2021-12-30

申请号：US16951595

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  H01L21/8239 ,  H01L27/11597 ,  G11C7/18

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US20210375990A1

公开(公告)日：2021-12-02

申请号：US17109427

申请日：2020-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Han-Jong Chia

IPC: H01L27/24 ,  H01L27/22 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.