公开(公告)号：US20250142932A1

公开(公告)日：2025-05-01

申请号：US19009221

申请日：2025-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10D64/23 ,  H10D30/01 ,  H10D62/17 ,  H10D64/01 ,  H10D64/27 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85

Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

公开(公告)号：US20240381656A1

公开(公告)日：2024-11-14

申请号：US18783024

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20240315044A1

公开(公告)日：2024-09-19

申请号：US18674134

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/40 ,  H01L21/8234 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/40 ,  H01L21/823475 ,  H01L23/5226 ,  H10B51/30

Abstract: Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.

公开(公告)号：US12022660B2

公开(公告)日：2024-06-25

申请号：US18447495

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/00 ,  H01L21/8234 ,  H01L23/522 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/40 ,  H01L21/823475 ,  H01L23/5226 ,  H10B51/30

Abstract: Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.

公开(公告)号：US11968828B2

公开(公告)日：2024-04-23

申请号：US16506823

申请日：2019-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42

CPC classification number: H10B41/42 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30 ,  H10B41/40

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile.

公开(公告)号：US11942475B2

公开(公告)日：2024-03-26

申请号：US16657396

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28052 ,  H01L21/823431 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US11910616B2

公开(公告)日：2024-02-20

申请号：US17818562

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L29/417 ,  H01L23/535 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L23/535 ,  H01L29/41741 ,  H01L29/41775 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US11903216B2

公开(公告)日：2024-02-13

申请号：US17744212

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H10B51/30

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11895836B2

公开(公告)日：2024-02-06

申请号：US17022390

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H10B41/10 ,  H10B41/50 ,  H01L29/423 ,  H01L29/51 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/28 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B41/50 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3212 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/518 ,  H10B41/10 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

公开(公告)号：US20240015982A1

公开(公告)日：2024-01-11

申请号：US18152597

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/30 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/30 ,  H01L29/78696 ,  H01L29/0847 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/6684 ,  H01L29/78391

Abstract: A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.