公开(公告)号：US20240313115A1

公开(公告)日：2024-09-19

申请号：US18670557

申请日：2024-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/511

Abstract: A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

公开(公告)号：US20210376092A1

公开(公告)日：2021-12-02

申请号：US17401970

申请日：2021-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20210327705A1

公开(公告)日：2021-10-21

申请号：US16851876

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu CHANG ,  Sai-Hooi YEONG ,  Yu-Ming LIN

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.

公开(公告)号：US20210249079A1

公开(公告)日：2021-08-12

申请号：US16785997

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong CHIA ,  Sai-Hooi YEONG ,  Yu-Ming LIN

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/419 ,  H01L27/11507 ,  H01L27/11 ,  H01L27/1159

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. There are more FRAM cells than SRAM cells. The first memory array and the second memory array share the same bus.

公开(公告)号：US20210225697A1

公开(公告)日：2021-07-22

申请号：US16744503

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive structure and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a second conductive structure partially surrounded by the second dielectric layer and partially surrounded by the first conductive structure. In addition, the semiconductor device structure includes an interfacial layer separating the first conductive structure from the second conductive structure.

公开(公告)号：US20210134669A1

公开(公告)日：2021-05-06

申请号：US16939994

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/522

Abstract: The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

公开(公告)号：US20210126129A1

公开(公告)日：2021-04-29

申请号：US16808770

申请日：2020-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.

公开(公告)号：US20210098368A1

公开(公告)日：2021-04-01

申请号：US16855690

申请日：2020-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a first metal via passing through the first insulating layer, and a second insulating layer formed over the first insulating layer. The semiconductor device structure also includes a first metal hump surrounded by the second insulating layer and connected to the top surface of the first metal via. The first metal hump covers the portion of the first insulating layer adjacent to the first metal via. In addition, the semiconductor device structure includes a metal line formed in the second insulating layer and electrically connected to the first metal via, and a conductive liner covering the first metal hump and separating the metal line from the second insulating layer and the first metal hump.

公开(公告)号：US20210057530A1

公开(公告)日：2021-02-25

申请号：US16546799

申请日：2019-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285

Abstract: A semiconductor device includes a substrate, a source/drain structure, a source/drain contact, a gate structure, a first etching stop layer, and a via contact. The source/drain structure is over the substrate. The source/drain contact is over the source/drain contact. The gate structure is over the substrate. The first etching stop layer is over the gate structure, in which the first etching stop layer includes a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion. The via contact extends along a top surface of the first portion of the first etching stop layer to a sidewall of the second portion of the first etching stop layer.

公开(公告)号：US20200343373A1

公开(公告)日：2020-10-29

申请号：US16856842

申请日：2020-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung TSAI ,  Clement Hsingjen WANN ,  Kuo-Feng YU ,  Yi-Tang LIN ,  Yu-Ming LIN

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.