DIGITAL TO ANALOG CONVERTER
    51.
    发明申请
    DIGITAL TO ANALOG CONVERTER 有权
    数字到模拟转换器

    公开(公告)号:US20130082853A1

    公开(公告)日:2013-04-04

    申请号:US13251935

    申请日:2011-10-03

    IPC分类号: H03M1/06 H03M3/02 H03M1/20

    摘要: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.

    摘要翻译: 公开了一种数模转换器。 该转换器包括梯度校正模块,该梯度校正模块基于梯度误差的模型产生校正项。 然后将校正项应用于数字域中的信号路径或应用于模拟域中的数模转换器的输出。 用于产生校正项的模型基于当前源元素阵列中的垂直梯度误差,其可以使用二阶多项式来建模和校准。 此外,公开了具有奈奎斯特DAC和过采样DAC的数模转换器。 当使能过采样DAC时,可能会增加奈奎斯特DAC的分辨率,同时降低转换速率。

    Digital charge pump PLL architecture
    53.
    发明授权
    Digital charge pump PLL architecture 有权
    数字电荷泵PLL架构

    公开(公告)号:US08004326B2

    公开(公告)日:2011-08-23

    申请号:US12515562

    申请日:2007-12-13

    IPC分类号: H03L7/06

    摘要: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

    摘要翻译: 一种具有数字电荷泵电路的数字锁相环(PLL)电路,用于提供对应于与压控振荡器相对应的内部时钟之间的相位差的数字信号和参考时钟。 这些数字信号由用于提供数字控制信号的数字处理电路处理。 一些数字控制信号被转换成模拟控制信号以提供压控振荡器的精细控制,而剩余的数字控制信号提供压控振荡器的粗略控制。

    Automatic IIP2 calibration architecture
    54.
    发明授权
    Automatic IIP2 calibration architecture 有权
    自动IIP2校准架构

    公开(公告)号:US07742747B2

    公开(公告)日:2010-06-22

    申请号:US11626964

    申请日:2007-01-25

    IPC分类号: H04B1/04 H04K3/00

    摘要: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

    摘要翻译: 公开了一种用于无线收发器的综合自动IIP2校准架构。 该架构使得无线收发器能够生成具有最小附加电路的具有二阶音调的测试射频(RF)信号。 特别地,使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路,其可用于产生测试(RF)信号。 测试适配器电路被添加到收发器芯片中,更具体地被添加到本地电路,用于使得本机电路能够以自测试操作模式生成测试RF信号。 用于实现特定的IIP2最小化方案的电路可以在自检操作模式下在收发器芯片中包括在自动IIP2校准中。

    Tuneable circuit for canceling third order modulation
    55.
    发明授权
    Tuneable circuit for canceling third order modulation 有权
    用于消除三阶调制的调谐电路

    公开(公告)号:US07710185B2

    公开(公告)日:2010-05-04

    申请号:US11569021

    申请日:2005-05-12

    申请人: Tajinder Manku

    发明人: Tajinder Manku

    IPC分类号: G06F7/44 G06G7/16

    摘要: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

    摘要翻译: 提供了用于消除三阶互调的CMOS跨导体。 跨导体包括跨导电路和可调谐失真电路。 跨导电路采用输入电压并产生具有跨导元件和IM3元件的输出电流。 失真电路采用相同的输入电压,并产生具有与跨导电路的IM3元件相等幅度和相反相位的IM3元件的电流。 控制器电路调谐失真电路以将其IM3元件调整为基本上等于跨导电路的IM3的振幅。 失真和跨导电路被布置为对其输出电流求和,从而有效地消除IM3元件,从而使跨导相对未被修改。

    DIGITAL LINEAR TRANSMITTER ARCHITECTURE
    56.
    发明申请
    DIGITAL LINEAR TRANSMITTER ARCHITECTURE 有权
    数字线性发射机架构

    公开(公告)号:US20100027711A1

    公开(公告)日:2010-02-04

    申请号:US12520486

    申请日:2007-12-14

    IPC分类号: H04L27/00 H03M1/66

    摘要: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (ΔΣ) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ΔΣ DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

    摘要翻译: 一种用于数字到模拟转换射频信号的数字线性发射机。 发射机在无线设备的发射路径中包括Δ西格玛(DeltaSigma)数模转换器(DAC)和加权信号数模转换器,以减少对相对大的模拟组件的依赖。 DeltaSigma DAC转换过采样信号的最低有效位,而加权信号数模转换器转换过采样信号的最高有效位。 发射机核心包括用于提供过采样的调制数字信号的组件,然后在产生相应的模拟信号之前对过采样信号进行一阶滤波。 该装置和方法减少了模拟组件并增加了无线RF设备的发射机核心架构中的数字组件。

    CLOSED-LOOP DIGITAL POWER CONTROL FOR A WIRELESS TRANSMITTER
    57.
    发明申请
    CLOSED-LOOP DIGITAL POWER CONTROL FOR A WIRELESS TRANSMITTER 有权
    无线发射机闭环数字功率控制

    公开(公告)号:US20100027596A1

    公开(公告)日:2010-02-04

    申请号:US12520448

    申请日:2007-12-21

    IPC分类号: H04B1/38

    CPC分类号: H03G3/3047 H04B2001/0416

    摘要: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

    摘要翻译: 一种用于可变功率输出无线设备的闭环功率输出校准系统。 无线设备包括具有耦合到分立功率放大器的发射芯的无线收发器。 在无线收发器中形成的功率检测电路提供功率放大器的检测功率电平和参考功率电平,两者都使用接收机核心中现有的I和Q信号模数转换器转换成数字信号。 处理数字信号以消除功率失真和温度影响,以提供最终的功率反馈信号。 响应于功率反馈信号相对于期望的功率输出电平产生校正控制信号。 然后响应于校正控制信号调整发送内核中的增益,使得功率放大器输出目标输出功率电平。

    Transceiver interface architecture
    58.
    发明申请
    Transceiver interface architecture 审中-公开
    收发器接口架构

    公开(公告)号:US20070223615A1

    公开(公告)日:2007-09-27

    申请号:US11387925

    申请日:2006-03-24

    IPC分类号: H04L1/02 H04B1/00

    CPC分类号: H04B1/50 H04B1/0057

    摘要: A transceiver interface architecture where the same RF transceiver can be used in wireless devices that support any number of standards, with or without receive diversity implementation. Each input port of the RF transceiver can be shared by a number of input signals, which effectively expands the number of available input ports. Input port sharing can be realized with virtual ports that receive two or more input signals and selectively pass one signal to the physical input port. The use of virtual ports allows for flexible wireless design implementations using the same RF transceiver, and in particular, for receive diversity implementations that inherently require dedicated input ports. The use of low cost and small area virtual ports obviates the need for larger and more costly RF receivers.

    摘要翻译: 收发器接口架构,其中相同的RF收发器可以在支持任何数量的标准的无线设备中使用,具有或不具有接收分集实现。 RF收发器的每个输入端口可以由多个输入信号共享,这有效地扩展了可用输入端口的数量。 可以通过接收两个或更多输入信号的虚拟端口实现输入端口共享,并选择性地将一个信号传递到物理输入端口。 虚拟端口的使用允许使用相同的RF收发器的灵活的无线设计实现,并且特别地,用于固有地需要专用输入端口的接收分集实现。 使用低成本和小面积的虚拟端口消除了对更大和更昂贵的RF接收机的需要。

    Method and apparatus for reduced noise band switching circuits
    59.
    发明申请
    Method and apparatus for reduced noise band switching circuits 失效
    用于降低噪声频带切换电路的方法和装置

    公开(公告)号:US20050134392A1

    公开(公告)日:2005-06-23

    申请号:US11018846

    申请日:2004-12-22

    摘要: A low-phase noise voltage control oscillator (VCO) comprising a voltage source for supplying control voltage to the VCO core; a phase lock loop, having an output connected to an input of the voltage source; a VCO core, including an amplifier circuit with noiseless biasing and a tank circuit with noiseless biasing of the varactors; having an output connected to an input of the phase lock loop; and an attenuator, located between the voltage source and the VCO core, for reducing phase noise from the voltage source to the VCO core.

    摘要翻译: 一种低相位噪声电压控制振荡器(VCO),包括用于向VCO核心提供控制电压的电压源; 锁相环,具有连接到电压源的输入的输出; VCO核心,包括具有无噪声偏置的放大器电路和具有无阻抗偏置的变容二极管的电路; 具有连接到所述锁相环的输入的输出; 以及位于电压源和VCO核心之间的衰减器,用于减小从电压源到VCO核心的相位噪声。

    Filters implemented in integrated circuits
    60.
    发明授权
    Filters implemented in integrated circuits 有权
    集成电路中实现的滤波器

    公开(公告)号:US06867665B2

    公开(公告)日:2005-03-15

    申请号:US09934339

    申请日:2001-08-21

    CPC分类号: H03H7/07

    摘要: An integrated RF filter for use at microwave frequencies comprising: an integrated circuit inductor with connected integrated circuit capacitors, arranged as a tank circuit, and an integrated circuit shunt resistor; the inductor, capacitors and resistor being interconnected in a bridge-T filter arrangement.

    摘要翻译: 一种用于微波频率的集成RF滤波器,包括:具有连接的集成电路电容器的集成电路电感器,布置为储能电路,以及集成电路分流电阻器; 电感器,电容器和电阻器以桥式T滤波器布置互连。