公开(公告)号：US08067804B2

公开(公告)日：2011-11-29

申请号：US11251911

申请日：2005-10-18

Applicant: Shigeto Maegawa ,  Takashi Ipposhi

Inventor： Shigeto Maegawa ,  Takashi Ipposhi

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/78615 ,  H01L29/78624

Abstract: The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.

Abstract translation: 本发明提供能够抑制身体浮动效应的半导体器件及其制造方法。 具有SOI结构的半导体器件包括硅衬底，形成在硅衬底上的掩埋绝缘层和形成在掩埋绝缘层上的半导体层。 半导体层具有第一导电类型的主体区域，第二导电类型的源极区域和第二导电类型的漏极区域，并且栅极电极形成在源极区域和漏极区域通孔之间的体区域上 栅氧化膜。 源极区域包括第二导电类型的延伸层和在其侧面与延伸层接触的硅化物层，并且在位于第二导电类型之间的边界部分中产生的耗尽层的区域上形成晶体缺陷区域 硅化物层和身体区域。

公开(公告)号：US07898032B2

公开(公告)日：2011-03-01

申请号：US11672487

申请日：2007-02-07

Applicant: Takaya Suzuki ,  Takashi Ipposhi

Inventor： Takaya Suzuki ,  Takashi Ipposhi

IPC: H01L27/12

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

Abstract translation: 本发明实现了半导体器件的小型化。 在第一绝缘膜上形成围绕半导体层的岛状半导体层和第二绝缘膜，并且由导电膜形成的电阻元件（例如，多晶硅电阻元件）被布置成重叠 到半导体层的上表面。

公开(公告)号：US07786534B2

公开(公告)日：2010-08-31

申请号：US12399062

申请日：2009-03-06

Applicant: Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L27/01

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract translation: 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US07675122B2

公开(公告)日：2010-03-09

申请号：US11889704

申请日：2007-08-15

Applicant: Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

Inventor： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract translation: 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

公开(公告)号：US07535062B2

公开(公告)日：2009-05-19

申请号：US11619874

申请日：2007-01-04

Applicant: Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L27/01

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract translation: 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US20090051009A1

公开(公告)日：2009-02-26

申请号：US12254026

申请日：2008-10-20

Applicant: Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L29/8605

CPC classification number: H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

Abstract: Formed on an insulator are an N− type semiconductor layer having a partial isolator formed on its surface and a P− type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain being N+ type semiconductor layers are provided on the semiconductor layer to form an NMOS transistor. A pn junction formed by the semiconductor layers is provided in a CMOS transistor made up of the transistors. The pn junction is positioned separately from the partial isolators where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction.

Abstract translation: 在绝缘体上形成有在其表面上形成有部分隔离体的N-型半导体层，以及在其表面上形成有部分隔离体的P-型半导体层。 源极/漏极是P +型半导体层，设置在半导体层上以形成PMOS晶体管。 源极/漏极是N +型半导体层，设置在半导体层上以形成NMOS晶体管。 由半导体层形成的pn结设置在由晶体管构成的CMOS晶体管中。 pn结与部分隔离器分开定位，因此晶体缺陷非常小。 因此，在pn结处漏电流非常低。

公开(公告)号：US07453135B2

公开(公告)日：2008-11-18

申请号：US11617936

申请日：2006-12-29

Applicant: Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L29/93

CPC classification number: H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

Abstract translation: 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

公开(公告)号：US07449749B2

公开(公告)日：2008-11-11

申请号：US11448827

申请日：2006-06-08

Applicant: Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract translation: 在绝缘体（9）上形成的是具有形成在其表面上的部分隔离体的N + O - 型半导体层（10）和具有形成在其上的P型 - 半导体层（20） 形成在其表面上的部分隔离器。 在半导体层（10）上设置有源极/漏极（11,12）作为P +型半导体层，形成PMOS晶体管（1）。 在半导体层（20）上设置有N +型半导体层的源极/漏极（21,22），以形成NMOS晶体管（2）。 由半导体层（10,20）形成的pn结（J 5）设置在由晶体管（1,2）构成的CMOS晶体管（100）中。 pn结（J 5）与部分隔离物（41,42）分开定位，因此晶体缺陷非常小。 因此，在pn结处漏电流非常低（J 5）。

公开(公告)号：US20080211035A1

公开(公告)日：2008-09-04

申请号：US11889704

申请日：2007-08-15

Applicant: Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

Inventor： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

IPC: H01L27/11

CPC classification number: H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract translation: 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

公开(公告)号：US20080128810A1

公开(公告)日：2008-06-05

申请号：US12003277

申请日：2007-12-21

Applicant: Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

IPC: H01L29/786

CPC classification number: H01L29/78615 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78609

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.