公开(公告)号：US06465341B1

公开(公告)日：2002-10-15

申请号：US09872465

申请日：2001-05-31

申请人： Shekhar Pramanick

发明人： Shekhar Pramanick

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes: providing a semiconductor with a dielectric layer formed thereon; forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said semiconductor, forming a conductive layer in said opening; removing said conductive layer to said dielectric layer; and forming a barrier layer over said conductive layer and said dielectric layer, said barrier layer made of a compound of silicon nitride with a third material compounded therein wherein said third material is modulated in amount through said layer of silicon nitride.

摘要翻译： 一种制造半导体器件的方法包括：提供其上形成有介电层的半导体; 在所述电介质层中形成开口，所述开口由所述电介质层的壁限定并暴露所述半导体的一部分，在所述开口中形成导电层; 将所述导电层去除到所述介电层; 以及在所述导电层和所述电介质层之上形成阻挡层，所述阻挡层由氮化硅化合物制成，其中第三种材料混合在其中，其中所述第三材料的量通过所述氮化硅层进行调制。

公开(公告)号：US06372563B1

公开(公告)日：2002-04-16

申请号：US09614894

申请日：2000-07-12

申请人： Zoran Krivokapic ,  Shekhar Pramanick

发明人： Zoran Krivokapic ,  Shekhar Pramanick

IPC分类号： H01L2100

CPC分类号： H01L21/28052 ,  H01L21/2022 ,  H01L21/28097 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66651

摘要： A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

摘要翻译： 具有体接触和硅化物栅的自对准SOI器件。 SOI器件使用诸如硅的普通衬底形成。 硅化物栅极是自对准的，并由镍和非晶硅的再结晶形成。 自对准硅化物栅极包括栅极接触区域，并且相对于栅极开口，源极和漏极区域以及氮化物隔离层自对准。 沉积在隔离层附近的镍间隔物和沉积在镍间隔物之间​​的非晶硅通过硅化工艺形成自对准的硅化物栅极。

公开(公告)号：US06361837B1

公开(公告)日：2002-03-26

申请号：US09232359

申请日：1999-01-15

申请人： Suzette K. Pangrle ,  Richard J. Huang ,  Shekhar Pramanick

发明人： Suzette K. Pangrle ,  Richard J. Huang ,  Shekhar Pramanick

IPC分类号： B05D306

摘要： The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

公开(公告)号：US06171949B2

公开(公告)日：2001-01-09

申请号：US09329155

申请日：1999-06-09

申请人： Lu You ,  Shekhar Pramanick

发明人： Lu You ,  Shekhar Pramanick

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/3143 ,  H01L21/318

摘要： A method for manufacturing an integrated circuit using damascene processes is provided in which conductive material surfaces subject to chemical-mechanical polishing are passivated after polishing with a dry, low energy, ion implantation passivating process to prevent oxidation and to eliminate a high dielectric constant protective layer. In particular, copper conductive material is subject to nitrogen implantation at or below 100 KeV to produce a protective copper nitride.

摘要翻译： 提供一种使用镶嵌工艺制造集成电路的方法，其中进行化学机械抛光的导电材料表面在用干燥，低能量的离子注入钝化工艺抛光后被钝化，以防止氧化并消除高介电常数保护层 。 特别地，铜导电材料在100KeV以下进行氮注入以产生保护性的氮化铜。

公开(公告)号：US6165902A

公开(公告)日：2000-12-26

申请号：US187520

申请日：1998-11-06

申请人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

发明人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC分类号： H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28568

摘要： Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

摘要翻译： 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US6147404A

公开(公告)日：2000-11-14

申请号：US317813

申请日：1999-05-24

申请人： Shekhar Pramanick ,  Dirk Brown ,  John A. Iacoponi

发明人： Shekhar Pramanick ,  Dirk Brown ,  John A. Iacoponi

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76847 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  Y10S257/915

摘要： An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

摘要翻译： 提供了一种集成电路及其制造方法，其中执行部分双镶嵌沉积以将屏障，晶种和导电层放置在两个互连通道之间的通孔的大部分中，然后用另外的阻挡物，种子 导电层，以防止互连通道和通孔之间的电迁移。

公开(公告)号：US6091123A

公开(公告)日：2000-07-18

申请号：US93580

申请日：1998-06-08

申请人： Zoran Krivokapic ,  Shekhar Pramanick

发明人： Zoran Krivokapic ,  Shekhar Pramanick

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/66651 ,  H01L21/2022 ,  H01L21/28097 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/4975

摘要： A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

公开(公告)号：US6046106A

公开(公告)日：2000-04-04

申请号：US924133

申请日：1997-09-05

申请人： Khanh Q. Tran ,  Paul R. Besser ,  Guarionex Morales ,  Shekhar Pramanick

发明人： Khanh Q. Tran ,  Paul R. Besser ,  Guarionex Morales ,  Shekhar Pramanick

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76834

摘要： Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.

摘要翻译： 在被填充有高密度等离子体氧化物的图案化金属层间隙之间形成无边界的亚微米通孔。 在高密度等离子体氧化物的化学气相沉积之后进行热处理，以显着增加图案化金属层的晶粒尺寸，从而提高抗电迁移性。

公开(公告)号：US6015752A

公开(公告)日：2000-01-18

申请号：US106769

申请日：1998-06-30

申请人： Qi Xiang ,  Shekhar Pramanick

发明人： Qi Xiang ,  Shekhar Pramanick

IPC分类号： H01L21/336 ,  H01L21/283 ,  H01L21/288

CPC分类号： H01L29/665 ,  H01L29/41783

摘要： Low resistivity metal silicide layers are formed on crystalline source/drain regions and polycrystalline gate electrodes with virtually no consumption of crystalline or polycrystalline silicon, thereby reducing parasitic series resistance without encountering junction leakage. Embodiments include selectively depositing a layer of nickel at a temperature less than about 280.degree. C. on the source/drain region and gate electrode, and then depositing a layer of amorphous silicon at a temperature below about 280.degree. C. thereon. An initial low temperature annealing is conducted, e.g., at about 180.degree. C. to about 280.degree. C., to react the amorphous silicon and nickel to form an upwardly grown layer of amorphous nickel silicide on the source/drain region and gate electrode with virtually no consumption of underlying silicon. Unreacted amorphous silicon is then removed, as by wet etching, and a second high temperature annealing is conducted to convert the high resistivity amorphous nickel silicide to low resistivity polycrystalline nickel silicide.

摘要翻译： 在结晶源极/漏极区域和多晶栅极电极上形成低电阻率金属硅化物层，实质上不消耗晶体或多晶硅，从而降低寄生串联电阻而不会遇到结漏电。 实施例包括在源极/漏极区域和栅极电极上选择性地在低于约280℃的温度下沉积镍层，然后在其上低于约280℃的温度沉积非晶硅层。 进行初始低温退火，例如在约180℃至约280℃，以使非晶硅和镍反应以在源极/漏极区域和栅电极上形成向上生长的非晶硅化镍层， 几乎没有消耗底层硅。 然后通过湿蚀刻除去未反应的非晶硅，并且进行第二次高温退火以将高电阻率非晶硅化镍转化为低电阻率多晶硅化镍。

公开(公告)号：US5994191A

公开(公告)日：1999-11-30

申请号：US112156

申请日：1998-07-09

申请人： Qi Xiang ,  Shekhar Pramanick

发明人： Qi Xiang ,  Shekhar Pramanick

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/66628 ,  H01L29/665 ,  Y10S148/147

摘要： Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.

摘要翻译： 低电阻金属硅化物层以最佳厚度形成在栅电极和源极/漏极区上，用于减少寄生串联电阻，伴随着来自栅电极和源极/漏极区的硅的消耗。 然后使用金属诱导结晶来代替来自栅电极和源/漏区的消耗硅，从而避免高漏电流。 实施例包括在金属硅化物层上沉积非晶硅层并在约400℃至约600℃的温度下加热，引发金属诱导结晶，从而使金属硅化物层向上生长，因为底层栅电极中的硅 并且更换源极/漏极区域。