公开(公告)号：US5418923A

公开(公告)日：1995-05-23

申请号：US937763

申请日：1992-09-01

申请人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

发明人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

摘要翻译： 当从联想存储器获得符合信号时，编码电路将一致信号所需的时间缩短为根据预定的优先级依次选择和输出之后被转换成地址码。 该电路设置有用于较低子组的竞争仲裁电路和用于较高子组的争用仲裁电路。 在用于较低子组的竞争仲裁电路和较高子组的竞争仲裁电路中，每个符合信号同时激活优先级低于一致信号的优先级的禁止信号。 在下一个子组的竞争仲裁电路中，按照降序排列下半部分的符合信号，并且在较高子组的竞争仲裁电路中按照升序排列较高的一半符号信号。 用于较低子组的争用仲裁电路和用于较高子组的争用仲裁电路分别以三角阵列和互补三角阵列排列。

公开(公告)号：US5388066A

公开(公告)日：1995-02-07

申请号：US084098

申请日：1993-07-01

申请人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G06F17/30 ,  G11C15/00 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

摘要： A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

摘要翻译： 一种数据存储电路，其特征在于，具备排列成多个行和列的存储单元以及对应于各行的标志单元，用于存储标志信息，存储单元和构成一个字的同一行的标志单元。 当外部应用检索数据时，将包括在检索数据中的数据与存储单元的数据进行比较，并将存储在检索数据中的标志信息与存储在标志单元中的标志进行比较。 比较结果输出到匹配行。 逻辑运算电路根据比较结果输出到匹配线进行逻辑运算，并将逻辑输出写入数据存储电路的标志单元。

公开(公告)号：US5319589A

公开(公告)日：1994-06-07

申请号：US966921

申请日：1992-10-27

申请人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

发明人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

IPC分类号： G11C15/00 ,  G11C11/4094 ,  G11C15/04 ,  G11C29/04

CPC分类号： G11C11/4094 ,  G11C15/043

摘要： A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

摘要翻译： 公开了一种用于实现动态内容可寻址存储器的位线控制电路。 位线控制电路包括读取电路12和连接到数据线对DT，/ DT的第一写入电路13，读出放大器14，位线放电电路15，位线充电电路16，传输门电路17 和第二写入电路18.位线控制电路通过位线BLa，/ BLa连接到CAM单元阵列。 可以通过简单的电路配置在简单的定时控制下，在动态关联存储器中所需的诸如写入，读取，刷新和匹配检测等各种操作。

公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

公开(公告)号：US09267585B2

公开(公告)日：2016-02-23

申请号：US13823193

申请日：2011-06-02

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： F16H19/08

CPC分类号： F16H19/08 ,  Y10T74/1888

摘要： Implementations and techniques are generally disclosed for an actuator comprising: a first element, a second element, a third element, a first joint provided between the first element and the second element, a second joint provided between the second element and the third element, and a motor operably coupled to the first joint and configured such that the second element rotates with respect to the first element about a first rotational axis when the motor rotates, wherein the first joint is operably coupled to the second joint and configured such that the third element can rotate with respect to the second element about a second rotational axis when the motor rotates.

摘要翻译： 通常公开了用于致动器的实现和技术，包括：第一元件，第二元件，第三元件，设置在第一元件和第二元件之间的第一接头，设置在第二元件和第三元件之间的第二接头，以及 电动机，其可操作地联接到所述第一接头并且被配置为使得当所述电动机旋转时，所述第二元件相对于所述第一元件围绕第一旋转轴线旋转，其中所述第一接头可操作地联接到所述第二接头并且被配置为使得所述第三元件 当电动机旋转时，它可相对于第二元件围绕第二旋转轴线旋转。

公开(公告)号：US20130238123A1

公开(公告)日：2013-09-12

申请号：US13702934

申请日：2012-03-12

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G06F19/00

CPC分类号： B62D57/02 ,  B25J9/102 ,  B62D57/032 ,  G06F19/00 ,  Y10S901/23 ,  Y10T74/20317

摘要： Embodiments provided herein generally relate to robotic limbs and uses thereof. In some embodiments, the motor for driving movement of the limb can itself be repositioned, thereby altering the forces and/or torque involved in moving and/or operating the limb.

公开(公告)号：US07312601B2

公开(公告)日：2007-12-25

申请号：US10945721

申请日：2004-09-21

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G05F3/04

CPC分类号： G05F1/468 ,  Y10S323/901

摘要： A circuit includes a current generator, a start-up circuit coupled to provide a start-up current to the current generator during a start-up phase of the current generator, and a cut-off circuit coupled to both the current generator and to the start-up circuit to provide a control signal that reduces the start-up current when an output current from the current generator exceeds a threshold value.

摘要翻译： 电路包括电流发生器，启动电路，其耦合以在电流发生器的启动阶段期间向电流发生器提供启动电流;以及截止电路，其耦合到电流发生器和至 启动电路以提供当来自电流发生器的输出电流超过阈值时降低启动电流的控制信号。

公开(公告)号：US20060061345A1

公开(公告)日：2006-03-23

申请号：US10945721

申请日：2004-09-21

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G05F3/04

CPC分类号： G05F1/468 ,  Y10S323/901

摘要： A circuit includes a current generator, a start-up circuit coupled to provide a start-up current to the current generator during a start-up phase of the current generator, and a cut-off circuit coupled to both the current generator and to the start-up circuit to provide a control signal that reduces the start-up current when an output current from the current generator exceeds a threshold value.

摘要翻译： 电路包括电流发生器，启动电路，其耦合以在电流发生器的启动阶段期间向电流发生器提供启动电流;以及截止电路，其耦合到电流发生器和至 启动电路以提供当来自电流发生器的输出电流超过阈值时降低启动电流的控制信号。

公开(公告)号：US06900628B2

公开(公告)日：2005-05-31

申请号：US10136398

申请日：2002-05-02

申请人： Hidenori Shirahama ,  Masaaki Mihara

发明人： Hidenori Shirahama ,  Masaaki Mihara

IPC分类号： H01L21/66 ,  G01R31/28 ,  H03K19/00 ,  G01R31/02

CPC分类号： G01R31/2853

摘要： In a pin contact test, a voltage across an external pin is measured by setting a voltage to be supplied to the power supply nodes in input protection circuits in their respective chips at a prescribed amount by means of voltage control circuits and by supplying a prescribed constant current to external pin. Based on the measurement results, a pin contact failure in chips can be detected.

摘要翻译： 在引脚接触测试中，通过设置通过电压控制电路将规定量的各个芯片中的输入保护电路中的输入保护电路中的电源节点设置为电压，并通过提供规定的常数来测量外部引脚上的电压 电流到外部引脚。 基于测量结果，可以检测到芯片中的引脚接触故障。

公开(公告)号：US06788581B2

公开(公告)日：2004-09-07

申请号：US10337342

申请日：2003-01-07

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G11C1606

CPC分类号： G11C16/26 ,  G11C16/24 ,  G11C16/28

摘要： A transistor operating as a current source supplying a memory cell with a current is configured to operate in a saturation range when a node subjected to a decision as to whether a memory cell has a high or low level has a voltage in a range of no more than a threshold voltage.