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公开(公告)号：US4965767A
公开(公告)日：1990-10-23
申请号：US380428
申请日：1989-07-17
IPC分类号： G11C15/04
CPC分类号： G11C15/043 , G11C15/04
摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.
摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。
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2.发明授权Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor 失效具有改进的堆叠电容器的半导体集成电路器件及其制造方法
公开(公告)号：US5146300A
公开(公告)日：1992-09-08
申请号：US830971
申请日：1992-02-10
IPC分类号： G11C15/04 , H01L27/108
CPC分类号： H01L27/108 , G11C15/043
摘要： A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.
摘要翻译： 一种半导体集成电路器件，包括：具有主表面的半导体衬底; 形成在所述主表面上的第一导电区域; 形成在所述主表面上的第二导电区域，与所述第一导电区域间隔开并且电连接到所述第一导电区域; 以及具有连接第一和第二导电区域的存储节点的电容器。 存储节点用于连接第一和第二导电区域并同时存储电荷。 在本发明的其他方面，提供了一种具有上述结构的存储单元，以及制造上述半导体集成电路器件的方法。
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3.发明授权
公开(公告)号：US5126968A
公开(公告)日：1992-06-30
申请号：US605707
申请日：1990-10-30
IPC分类号： G11C15/04
CPC分类号： G11C15/043 , G11C15/04
摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.
摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。
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4.发明授权Content addressable memory combining match comparisons of a plurality of cells 失效内容可寻址存储器组合多个单元的比较比较
公开(公告)号：US5130945A
公开(公告)日：1992-07-14
申请号：US551268
申请日：1990-07-12
CPC分类号： G11C15/04 , G11C15/043
摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.
摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。
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公开(公告)号：US4998027A
公开(公告)日：1991-03-05
申请号：US491014
申请日：1990-03-09
IPC分类号： G06F13/362 , G06F13/364 , H03K17/00
CPC分类号： G06F13/364
摘要： Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the "negative acknowledgement" and a signal of the logical level L indicating the "acknowledgement" are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.
摘要翻译： 公开了一种用于仲裁同时达到表示“请求”的H（逻辑高）电平的两个请求信号之间的争用的仲裁电路。 在该仲裁器电路中，具有不同输入逻辑阈值电压的缓冲电路连接到两个三输入NAND门的相应输出。 这两个缓冲电路的各自的输出，作为指示请求信号的“确认”或“否定确认”的信号被导出为仲裁器电路的最终输出。 其中一个缓冲电路具有低于两个NAND门的逻辑阈值电压的输入逻辑阈值电压，而另一个缓冲电路的输入逻辑阈值电压设置为高于NAND门的逻辑门限电压。 因此，当NAND门不产生具有H电平和L（逻辑低）电平的逻辑电平的电压时，指示“否定确认”的逻辑电平H的信号和表示“ 确认“能够从具有较低输入逻辑阈值电压的缓冲电路和具有较高输入逻辑阈值电压的另一缓冲电路可靠地输出。 也就是说，即使两个请求同时发生，一个请求信号被快速确认。
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6.发明授权Arbiter circuit for processing concurrent requests for access to shared resources 失效仲裁器电路，用于处理共享资源访问的并发请求
公开(公告)号：US4924220A
公开(公告)日：1990-05-08
申请号：US286922
申请日：1988-11-18
IPC分类号： G06F15/16 , G06F13/14 , G06F13/362 , G06F13/364 , G06F15/177
CPC分类号： G06F13/14 , G06F13/364
摘要： An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.
摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中由两个子系统同时进行的对共享资源的访问的竞争请求。 仲裁器电路包括由一对NAND门组成的SR触发器，并且在来自另一个子系统的请求信号之后的预定时间间隔期间阻止后续请求信号从一个子系统到SR触发器的通过 已被提供给触发器。 结果是，通过同时生成来自两个子系统的请求信号，SR触发器的两个输入都不会从低电平向上移动到高电平，从而消除了从翻转的输出的任何可能性 - 浮动在高低位之间的中间水平。
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公开(公告)号：US5481496A
公开(公告)日：1996-01-02
申请号：US236004
申请日：1994-05-02
CPC分类号： G11C7/065 , G11C7/1006 , G11C7/12
摘要： Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.
摘要翻译： 为每个位线对提供的感测放大器被分成要被独立驱动的组，由此可以防止不同组的读出放大器的影响，因此数据传送期间未选择的存储器单元的数据的破坏可以是 防止了 在将数据从数据寄存器传送到存储单元阵列时，读出放大器不会被激活，直到由字线选择的存储单元的存储信息被完全读出到相应的位线为止， 可以防止选择的存储单元。
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公开(公告)号：US06344622B1
公开(公告)日：2002-02-05
申请号：US09626908
申请日：2000-07-27
IPC分类号： H01H900
CPC分类号： H01H13/70 , H01H2011/0081 , H01H2221/018 , H01H2223/002
摘要： A switch device includes a key member (4). The key member (4) has a display switch button (13) including a transparent portion through which image information displayed on a display screen of an image display device is transmitted so as to display the image information on an outer side surface of the key member (4). Further, the key member (4) has a button mounting frame (16) including a switch depressing portion (14) operative to switch a switch (6) when the key depressing portion (14) is depressed, and having a button mounting hole portion to which the display switch button (13) is attached. Furthermore, the key member (4) has a waterproof dust cover (19) of a rubber material, which is molded integrally on the button mounting frame (16) to cover the same, and which includes a support portion (17) held in intimate contact with the display screen, and a contractible skirt portion (18). A plurality of resin filling holes are formed in the button mounting frame. The rubber material, forming the waterproof dust cover (19), is filled in the resin filling holes.
摘要翻译： 开关装置包括键构件（4）。 键构件（4）具有显示开关按钮（13），其包括透明部分，通过该透明部分发送显示在图像显示装置的显示屏幕上的图像信息，以便在键部件的外侧表面上显示图像信息 （4）。 此外，键构件（4）具有按钮安装框架（16），该按钮安装框架（16）包括当按压键按压部（14）时可操作地切换开关（6）的开关按压部（14），并且具有按钮安装孔部 显示开关按钮（13）附接到该显示开关按钮。 此外，键构件（4）具有橡胶材料的防水防尘罩（19），其一体地模制在按钮安装框架（16）上以覆盖其上，并且包括保持在亲密的支撑部分（17） 与显示屏幕接触，以及收缩裙部分（18）。 多个树脂填充孔形成在按钮安装框架中。 形成防水防尘罩（19）的橡胶材料填充在树脂填充孔中。
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9.发明授权Arbiter circuit for processing concurrent requests for access to shared resources 失效仲裁器电路，用于处理共享资源访问的并发请求
公开(公告)号：US4962379A
公开(公告)日：1990-10-09
申请号：US286921
申请日：1988-11-18
IPC分类号： G06F15/16 , G06F9/48 , G06F13/362 , G06F13/364 , G06F15/177 , H03K3/037 , H03K17/00
CPC分类号： G06F13/364
摘要： An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources. Thus, one of the two subsystems is allowed access to the shared resource.
摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中至少两个子系统的请求，以访问子系统共享的资源。 仲裁器电路包括由一对NAND门构成的SR触发器。 触发器响应于来自子系统的时间错误的请求信号而工作，以向共享资源提供请求确认信号。 当两个请求信号同时提供给仲裁器电路时，来自该对NAND门的输出趋向于保持在正常的两个不平等逻辑电平之间的中间电平，不能产生确认信号。 然而，NAND门输出的中间电平由或非门触发，触发开关器件进入导通状态，通过其中的一个中间NAND门输出被积极地移动到任何一个有源逻辑电平以产生 向共享资源发送确认信号。 因此，允许两个子系统之一访问共享资源。
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公开(公告)号：US4689770A
公开(公告)日：1987-08-25
申请号：US792071
申请日：1985-10-28
IPC分类号： G11C11/401 , G11C5/02 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24
CPC分类号： G11C5/025 , G11C11/4097 , G11C7/18 , H01L2924/0002
摘要： An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.
摘要翻译： 基本上消除了读出连接到器件的存储单元阵列的最外位线的存储单元的错误的LSI半导体存储器件。 根据本发明，这是通过使与存储单元阵列中相应的位线相关联的电容基本上彼此相等来实现的。 为了实现这一点，使除阵列的位线之外的布线的内部部分的配置与位线的配置相同，并且使最外侧位线和其它布线之间的距离等于 相邻的位线。
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