公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

公开(公告)号：US08581302B2

公开(公告)日：2013-11-12

申请号：US13295053

申请日：2011-11-12

申请人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

发明人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

IPC分类号： H01L27/118

CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

公开(公告)号：US06337506B2

公开(公告)日：2002-01-08

申请号：US09116887

申请日：1998-07-16

申请人： Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Mitsuya Kinoshita ,  Mako Kobayashi

发明人： Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Mitsuya Kinoshita ,  Mako Kobayashi

IPC分类号： H01L2900

CPC分类号： H01L23/552 ,  G11C5/14 ,  H01L21/761 ,  H01L23/585 ,  H01L27/0203 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

摘要翻译： 噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。 提供保护环以至少部分地具有接合焊盘。 利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

公开(公告)号：US6084386A

公开(公告)日：2000-07-04

申请号：US362665

申请日：1999-07-29

申请人： Mitsue Takahashi ,  Tadaaki Yamauchi ,  Mitsuya Kinoshita

发明人： Mitsue Takahashi ,  Tadaaki Yamauchi ,  Mitsuya Kinoshita

IPC分类号： G11C11/413 ,  G05F1/565 ,  G11C11/407 ,  H02M3/137 ,  G05F1/40 ,  G05F1/56

CPC分类号： G05F1/565

摘要： A voltage generation circuit includes a voltage comparing circuit to compare a reference voltage signal Vi and an internal power supply voltage Vcc and a current supply transistor to supply current based on the output voltage of the voltage comparing circuit and maintain Vcc. The voltage generation circuit also includes a reference voltage signal generation circuit which responds to a control signal ACT activated for a prescribed time period prior to the operation timing of a load and sets Vi=Vref when control signal ACT is inactive and Vi=Vref+.DELTA.V when control signal ACT is active.

摘要翻译： 电压产生电路包括用于比较参考电压信号Vi和内部电源电压Vcc的电压比较电路和电流源晶体管，以基于电压比较电路的输出电压提供电流并维持Vcc。 电压产生电路还包括参考电压信号产生电路，其响应于在负载的操作定时之前的规定时间段内激活的控制信号ACT，并且当控制信号ACT无效时设置Vi = Vref，并且Vi = Vref + DELTA V 当控制信号ACT有效时。

公开(公告)号：US5321654A

公开(公告)日：1994-06-14

申请号：US863975

申请日：1992-04-06

申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C8/18

摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

摘要翻译： 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

公开(公告)号：US5279984A

公开(公告)日：1994-01-18

申请号：US45161

申请日：1993-04-12

申请人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

发明人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L27/118 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76894 ,  H01L23/5258 ,  H01L27/118 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device in which circuit functions can be remedied or changed by severing at least a portion of a circuit pattern and a method for producing such semiconductor integrated circuit device. The circuit pattern is formed on the semiconductor substrate. A field shield plate is formed on the major surface of the semiconductor substrate for electrically separating respective elements constituting the circuit. The circuit pattern includes a fuse element. The fuse element is provided on the field shield plate. The portion of the field shield plate lying directly below the fuse element is isolated from other portions of the field shield plate. In such semiconductor integrated circuit device, the portion of the field shield plate lying directly below the fuse element is separated from other portions of the field shield plate, so that short-circuiting between the semiconductor substrate and the field shield plate cannot occur even when the laser beam is irradiated with a laser beam deviation at the time of severing of the fuse element.

摘要翻译： 一种半导体集成电路器件，其中可以通过切断电路图案的至少一部分来补救或改变电路功能，以及用于制造这种半导体集成电路器件的方法。 电路图案形成在半导体衬底上。 在半导体基板的主表面上形成场屏蔽板，用于电分离构成电路的各个元件。 电路图案包括熔丝元件。 保险丝元件设置在场屏蔽板上。 位于保险丝元件正下方的场屏蔽板的部分与场屏蔽板的其它部分隔离。 在这样的半导体集成电路器件中，位于熔丝元件正下方的场屏蔽板的部分与场屏蔽板的其他部分分离，使得半导体衬底和场屏蔽板之间的短路即使在 激光束在熔断元件断开时被激光束的偏离照射。

公开(公告)号：US06854078B2

公开(公告)日：2005-02-08

申请号：US09987563

申请日：2001-11-15

申请人： Mitsuya Kinoshita ,  Katsumi Dosaka

发明人： Mitsuya Kinoshita ,  Katsumi Dosaka

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C29/34 ,  G11C29/40 ,  G11C29/00

CPC分类号： G11C29/40 ,  G11C29/34

摘要： Internal read out data bits are divided into a plurality of data groups, and data bits in corresponding positions in different data groups are paired off. A determination gate is provided to each pair of data bits, and determining operation is performed in each pair to compress the result of determination to finally generate a 1-bit flag indicating a match/mismatch in logic level among the internal read out data. Consequently, a multi-bit test circuit that has a reduced layout area and can perform high-speed multi-bit determination is provided.

摘要翻译： 内部读出数据位被分成多个数据组，并且不同数据组中对应位置的数据位被配对。 向每对数据比特提供确定门，并且在每一对中执行确定操作以压缩确定结果，以最终产生指示内部读出数据中逻辑电平的匹配/不匹配的1比特标志。 因此，提供了具有减少的布局面积并且可以执行高速多位确定的多位测试电路。

公开(公告)号：US5914907A

公开(公告)日：1999-06-22

申请号：US122760

申请日：1998-07-27

申请人： Mako Kobayashi ,  Tetsushi Tanizaki ,  Kazutami Arimoto ,  Teruhiko Amano ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Mitsuya Kinoshita

发明人： Mako Kobayashi ,  Tetsushi Tanizaki ,  Kazutami Arimoto ,  Teruhiko Amano ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Mitsuya Kinoshita

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C29/42 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/84

摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.

摘要翻译： 常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。 位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。 为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。

公开(公告)号：US5578861A

公开(公告)日：1996-11-26

申请号：US357298

申请日：1994-12-13

申请人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

发明人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/10 ,  H01L23/62 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： In a semiconductor device, a connection conductive layer is formed by patterning on a p-type semiconductor substrate. A silicon nitride film is formed on the connection conductive layer with an insulating layer. A silicon oxide film is formed on the silicon nitride film. The silicon oxide film is provided with a hole. The silicon nitride film is exposed at a bottom of the hole. The hole is located immediately above the connection conductive layer. Thereby, a thickness of the insulating layer on a fuse element which can be blown can be controlled easily in the semiconductor device.

摘要翻译： 在半导体器件中，通过在p型半导体衬底上图案化形成连接导电层。 在具有绝缘层的连接导电层上形成氮化硅膜。 在氮化硅膜上形成氧化硅膜。 氧化硅膜设置有孔。 氮化硅膜暴露在孔的底部。 孔位于连接导电层的正上方。 由此，可以在半导体器件中容易地控制能够熔断的熔丝元件上的绝缘层的厚度。

公开(公告)号：US5574729A

公开(公告)日：1996-11-12

申请号：US338817

申请日：1994-11-10

申请人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

发明人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

CPC分类号： G11C29/848

摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

摘要翻译： 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。