公开(公告)号：US07800131B2

公开(公告)日：2010-09-21

申请号：US11921857

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/404 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极 （118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠 （113）表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。

公开(公告)号：US20090173968A1

公开(公告)日：2009-07-09

申请号：US12097700

申请日：2006-12-12

申请人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

发明人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

IPC分类号： H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.

摘要翻译： 半导体器件100包含未掺杂的GaN沟道层105，设置在与其接触的未掺杂的GaN沟道层105上的AlGaN电子供体层106，设置在AlGaN电子供体层106上的未掺杂的GaN层107，源电极 101和设置在未掺杂的GaN层107上彼此间隔开的漏电极103，设置在源电极101和漏电极103之间的区域中的凹槽111延伸穿过未掺杂的GaN层107，栅极 埋入凹槽111中的电极102与其底表面上的AlGaN电子供体层106接触，以及设置在未掺杂的GaN层107上的SiN膜108，在栅电极102和漏极之间的区域 103。

公开(公告)号：US20130069071A1

公开(公告)日：2013-03-21

申请号：US13553759

申请日：2012-07-19

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/778 ,  H01L29/205

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。

公开(公告)号：US08716755B2

公开(公告)日：2014-05-06

申请号：US13553759

申请日：2012-07-19

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。

公开(公告)号：US20130037868A1

公开(公告)日：2013-02-14

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US09123739B2

公开(公告)日：2015-09-01

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/737 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US20090230429A1

公开(公告)日：2009-09-17

申请号：US11921854

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tasuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tasuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 在高电压运行和高频下表现出良好性能的场效应晶体管（100）包括第一场极板电极（116）和第二场板电极（118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的横截面视图中，第二场板电极（118）与包括第一场极板电极和栅电极的结构的上部重叠的重叠区域的栅极长度方向上的长度（ 113）被指定为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

公开(公告)号：US20140084300A1

公开(公告)日：2014-03-27

申请号：US14117763

申请日：2012-05-15

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/778 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

摘要翻译： 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US08928038B2

公开(公告)日：2015-01-06

申请号：US14117763

申请日：2012-05-15

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

摘要翻译： 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US20130105811A1

公开(公告)日：2013-05-02

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面分别为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。