公开(公告)号：US20120012930A1

公开(公告)日：2012-01-19

申请号：US13109233

申请日：2011-05-17

申请人： Kumiko Sato ,  Hirofumi Hirasozu ,  Tomoko Matsudai

发明人： Kumiko Sato ,  Hirofumi Hirasozu ,  Tomoko Matsudai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors. The substrate has a first conductivity type. The first and second transistors are provided on the substrate. The first and second transistors each include a gate electrode provided on the substrate, a gate insulating film provided between the substrate and the gate electrode, a source and a drain region of a second conductivity type, and a high-concentration channel region of the first conductivity type. The source and drain regions are provided in regions of an upper portion of the substrate. A region directly under the gate electrode is interposed between the regions. The high-concentration channel region is formed on a side of the source region of the region of the upper portion directly under the gate electrode. The high-concentration channel region has an effective impurity concentration higher than that of the upper portion.

摘要翻译： 根据一个实施例，半导体器件包括半导体衬底以及第一和第二晶体管。 衬底具有第一导电类型。 第一和第二晶体管设置在基板上。 第一和第二晶体管各自包括设置在基板上的栅极电极，设置在基板和栅电极之间的栅极绝缘膜，第二导电类型的源极和漏极区域以及第一导电类型的高浓度沟道区域 导电类型。 源极和漏极区域设置在衬底的上部的区域中。 位于该栅极电极正下方的区域之间。 高浓度沟道区域形成在栅电极正下方的上部区域的源区的一侧。 高浓度通道区域的有效杂质浓度高于上部区域。

公开(公告)号：US20080315305A1

公开(公告)日：2008-12-25

申请号：US12141386

申请日：2008-06-18

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/2652 ,  H01L21/2658 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

摘要翻译： 第二导电类型的LDD层位于侧壁绝缘膜下面的半导体层的表面。 第二导电类型的源极层在与LDD层相邻的位置处形成在半导体层的表面中。 在半导体层的表面上，在与LDD层夹着栅电极的位置处形成第二导电类型的复层。 第二导电类型的漏极层在与复层层相邻的位置处形成在半导体层的表面中。 再次形成深度为半导体层表面的第一和第二杂质浓度的峰值。 第一杂质浓度的峰值小于第二杂质浓度的峰值。

公开(公告)号：US20070034894A1

公开(公告)日：2007-02-15

申请号：US11501715

申请日：2006-08-10

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/74

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US08664692B2

公开(公告)日：2014-03-04

申请号：US13600097

申请日：2012-08-30

申请人： Tsuneo Ogura ,  Tomoko Matsudai ,  Yuichi Oshino

发明人： Tsuneo Ogura ,  Tomoko Matsudai ,  Yuichi Oshino

IPC分类号： H01L29/739 ,  H01L29/73

CPC分类号： H01L29/36 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/861

摘要： According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.

摘要翻译： 根据一个实施例，半导体器件包括第一电极，第一导电型阴极层，第一导电型基极层，第二导电型阳极层，第二导电类型半导体层，第一导电类型半导体层，埋入 主体和第二电极。 第一导电类型半导体层在第一方向上与第二导电类型半导体层邻接，并且在与第一方向垂直的第二方向上在阳极层的表面上延伸。 埋藏体包括底部和侧壁部分。 底部与基层接触。 侧壁部与基底层，阳极层，第二导电型半导体层和第一导电型半导体层接触。 埋藏体沿第一方向延伸。

公开(公告)号：US08212310B2

公开(公告)日：2012-07-03

申请号：US13022611

申请日：2011-02-07

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US08110924B2

公开(公告)日：2012-02-07

申请号：US12408390

申请日：2009-03-20

申请人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Daisuke Minohara

发明人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Daisuke Minohara

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/585 ,  H01L23/522 ,  H01L23/552 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.

摘要翻译： 在DC-DC转换器中，在硅衬底上设置多层布线层，并且在硅衬底和多层布线层中形成控制输入电路和输出电路的控制电路。 此外，设置覆盖多层布线层的密封树脂层和连接到多层布线层的最上布线的连接构件，其穿透密封树脂层并具有从密封树脂层的上表面突出的上端部。 连接构件的上端部由突出电极形成。 与输出电路的端子连接的连接构件的水平横截面面积大于与控制电路的端子连接的连接构件的水平截面积。

公开(公告)号：US08067801B2

公开(公告)日：2011-11-29

申请号：US12181692

申请日：2008-07-29

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/735

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

摘要翻译： 提供了一种半导体器件，其包括形成在半导体层中的第一晶体管和第二晶体管。 第一晶体管包括第一源极区域和与第一源极区域夹持第一栅电极的第一漏极区域。 第二晶体管包括LDD区和漂移区，其夹持具有LDD区的第二栅极，以及与漂移区相邻的第二漏极区，以将第二栅电极夹在第二源极区。 第一栅电极具有形成在其侧面上的第一侧壁，并且第二栅电极具有形成在其侧面上的第二侧壁。 沿着第一绝缘体的前者的宽度与第二绝缘体的宽度不同。

公开(公告)号：US20110095369A1

公开(公告)日：2011-04-28

申请号：US12878979

申请日：2010-09-09

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

IPC分类号： H01L29/772

CPC分类号： H01L29/0692 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.

摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

公开(公告)号：US07906808B2

公开(公告)日：2011-03-15

申请号：US12476147

申请日：2009-06-01

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US20100176449A1

公开(公告)日：2010-07-15

申请号：US12688459

申请日：2010-01-15

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/266 ,  H01L21/823425 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device, includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, the second semiconductor region having a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the first semiconductor region; a source region of a second conductivity type provided on the first semiconductor region; a drain region of the second conductivity type provided on the second semiconductor region; an insulating film provided on the semiconductor layer between the source region and the drain region; a gate electrode provided on the insulating film; and a drift region of the second conductivity type provided in a surface side portion of the semiconductor layer between the gate electrode and the drain region, the drift region being in contact with the drain region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the drain region.

摘要翻译： 一种半导体器件，包括：半导体层，包括第一导电类型的第一半导体区域和第一导电类型的第二半导体区域，所述第二半导体区域具有低于第一导电类型杂质浓度的第一导电类型杂质浓度 第一个半导体区域; 设置在第一半导体区域上的第二导电类型的源极区域; 设置在所述第二半导体区域上的所述第二导电类型的漏极区域; 设置在源极区域和漏极区域之间的半导体层上的绝缘膜; 设置在绝缘膜上的栅电极; 以及设置在所述半导体层的栅极电极和漏极区域的表面侧部分中的所述第二导电类型的漂移区域，所述漂移区域与所述漏极区域接触并且具有低于第二导电型杂质浓度的第二导电类型杂质浓度 漏极区的导电型杂质浓度。