公开(公告)号：US09761657B2

公开(公告)日：2017-09-12

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/78 ,  G06F17/50 ,  H01L23/535

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US09570451B1

公开(公告)日：2017-02-14

申请号：US15151483

申请日：2016-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Tun-Jen Cheng

IPC: H01L21/338 ,  H01L27/11 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265

CPC classification number: H01L27/1116 ,  H01L21/0273 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1104 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492

Abstract: A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.

Abstract translation: 一种形成半导体器件的方法。 首先，提供基板，并且以掩模图案限定第一注入区域和第二注入区域。 随后，使用掩模图案对衬底上的抗蚀剂层进行构图，以形成暴露第一注入区域的第一开口和暴露第二注入区域的第二开口。 之后，处理包括部分阴离子离子注入的离子注入工艺，其中通过部分阴离子注入将第二注入区植入预定浓度，并且第一注入区基本上不被部分阴离子注入植入。

公开(公告)号：US09490316B2

公开(公告)日：2016-11-08

申请号：US14542672

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang ,  Shih-Yin Hsiao

IPC: H01L21/31 ,  H01L21/469 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，设置在衬底上的氧化硅层和覆盖氧化硅层的栅电极的至少一部分。 氧化硅层的上表面为多个山丘的形状。 氧化硅层可以为半导体结构提供低导通电阻。

公开(公告)号：US09406771B1

公开(公告)日：2016-08-02

申请号：US14854161

申请日：2015-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Ching-Chung Yang

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/4983 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/7833

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基板; 第一导电类型的第一和第二离子注入区域; 在第一和第二离子注入区域中形成的源极和漏极扩散区域; 形成在第一和第二离子注入区之间的沟道扩散区; 栅极层，其设置在所述沟道扩散区域的上方且位于所述源极和漏极扩散区域之间; 以及形成在所述栅极层中的沿第一方向延伸的第二导电类型的第三离子注入区。 第三离子注入区域位于沟道扩散区域的上方并覆盖两个侧面部分，两个侧面部分与沟道扩散区域的垂直于第一方向的第二方向延伸的两个边缘相邻。

公开(公告)号：US20150060980A1

公开(公告)日：2015-03-05

申请号：US14010611

申请日：2013-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ze-Wei Jhou ,  Ching-Chung Yang

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7889 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7885

Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.

Abstract translation: 提供了一种可编程装置及其制造方法。 可编程器件包括具有源极区，漏极区和邻近源极区和漏极区的扩散区的衬底; 耦合源极区和漏极区的沟道; 由导电材料形成并位于衬底上并对应于沟道的浮动栅; 以及形成在所述基板的所述扩散区域中的沟槽，其中所述浮栅延伸到所述沟槽，并且所述导电材料覆盖所述沟槽的侧壁。