公开(公告)号：US20250014941A1

公开(公告)日：2025-01-09

申请号：US18227991

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yuan Wen ,  Lung-En Kuo ,  Chung-Yi Chiu

IPC: H01L21/762

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

公开(公告)号：US12193342B2

公开(公告)日：2025-01-07

申请号：US18239108

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

公开(公告)号：US20240107777A1

公开(公告)日：2024-03-28

申请号：US17964935

申请日：2022-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Hung-Chan Lin ,  Chung-Yi Chiu

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L27/228 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

公开(公告)号：US20240032434A1

公开(公告)日：2024-01-25

申请号：US18376840

申请日：2023-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.

公开(公告)号：US20230411489A1

公开(公告)日：2023-12-21

申请号：US17868753

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L29/7833 ,  H01L29/41775 ,  H01L29/66492 ,  H01L29/401

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20230377952A1

公开(公告)日：2023-11-23

申请号：US17835983

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76813 ,  H01L21/304 ,  H01L21/31056 ,  H01L21/31144

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

公开(公告)号：US11825751B2

公开(公告)日：2023-11-21

申请号：US17377367

申请日：2021-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

公开(公告)号：US11785867B2

公开(公告)日：2023-10-10

申请号：US17372528

申请日：2021-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/00 ,  H10N70/011 ,  H10N70/231

Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.

公开(公告)号：US20220399492A1

公开(公告)日：2022-12-15

申请号：US17372528

申请日：2021-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.

公开(公告)号：US10121827B1

公开(公告)日：2018-11-06

申请号：US15813173

申请日：2017-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Fu Lin ,  Chung-Yi Chiu

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/16 ,  H01L29/24 ,  H01L29/49 ,  H01L29/786

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.