公开(公告)号：US08503185B2

公开(公告)日：2013-08-06

申请号：US13189461

申请日：2011-07-22

申请人： Joseph Huang

发明人： Joseph Huang

IPC分类号： G06F1/16

CPC分类号： G06K19/07732

摘要： A bookmark memory stick includes a PC board, a flat, elongated insulative holder shell having a recessed accommodation portion accommodating the PC board and a retaining hole disposed near the top end thereof, a metal cover shell surrounding the insulative holder shell and a clip, which has a transverse locating base fitted into a locating notch at the top end of the insulative holder shell, a double-bevelled clamping plate obliquely downwardly extended from the front side of the transverse locating base toward the inside of the metal cover shell and stopped against a inverted T-plate of the insulative holder shell and then curved obliquely outwardly for clamping a sheet member on the inverted T-plate, a back plate extended from the back side of the transverse locating base and inserted into the inner top side of the metal cover shell, and a hook plate obliquely extended from the back plate and engaged into the retaining hole of the insulative holder shell.

摘要翻译： 书签记忆棒包括PC板，平坦的细长绝缘保持壳，具有容纳PC板的凹入容纳部分和设置在其顶端附近的保持孔，围绕绝缘保持器壳体的金属盖壳和夹子， 具有安装在绝缘保持器壳体的顶端的定位槽口中的横向定位基座，从横向定位基座的前侧朝向金属盖壳体的内侧倾斜向下延伸的双斜面夹紧板， 倒置的T形板，然后向斜面向外弯曲，以将片状构件夹紧在倒置的T形板上，后板从横向定位基座的后侧延伸并插入金属盖的内侧顶部 壳体和从背板倾斜延伸并接合到绝缘保持器壳体的保持孔中的钩板。

公开(公告)号：US08237475B1

公开(公告)日：2012-08-07

申请号：US12248031

申请日：2008-10-08

申请人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

发明人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

IPC分类号： H03L7/06

CPC分类号： H03L7/0805 ,  H03L7/0814 ,  H03L7/0816

摘要： A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

摘要翻译： 电路包括锁定环和相位偏移电路。 锁定环产生用于控制锁定环路中的第一延迟的第一控制信号。 相位偏移电路延迟由第二控制信号控制的第二延迟的输入信号以产生延迟的信号。 相位偏移电路通过调整第一控制信号来产生第二控制信号，以提高相对于目标相位的延迟信号的精度。 第二控制信号补偿由电路的过程，电源电压和温度中的至少一个的变化引起的第二延迟的变化的至少一部分。

公开(公告)号：US08192211B1

公开(公告)日：2012-06-05

申请号：US13015569

申请日：2011-01-27

申请人： Joseph Huang

发明人： Joseph Huang

IPC分类号： H01R13/60

CPC分类号： H01R13/447 ,  H01R13/6658 ,  H05K5/0278

摘要： A retractable USB memory stick includes a metal casing having a longitudinal sliding slot, first and second locating holes located on opposing ends of the longitudinal sliding slot and a hook located on the rear side and defining an access gap, a PC board having a USB plug and a memory IC board, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a sliding block supported on a spring strip and inserted into the longitudinal sliding slot of the metal casing, retaining blocks protruded from the sliding block for selectively engaging the first locating hole or second locating hole to lock the insulation PC board holder to the metal casing in extended or received positions, and a latch located on the rear side and movable with the insulation PC board holder to close/open the access gap.

摘要翻译： 可伸缩的USB记忆棒包括具有纵向滑动槽的金属壳体，位于纵向滑动槽的相对端上的第一和第二定位孔以及位于后侧并限定出入隙的钩子，具有USB插头的PC板 以及保持PC板并可滑动地安装在金属外壳中的绝缘PC板支架。 绝缘PC板支架具有支撑在弹簧带上并滑入金属壳体的纵向滑动槽中的滑动块，从滑块突出的保持块，用于选择性地接合第一定位孔或第二定位孔以锁定绝缘PC板 保持器延伸到接收位置的金属外壳，以及位于后侧的闩锁，并且可与绝缘PC板支架一起移动以关闭/打开进入间隙。

公开(公告)号：USD655709S1

公开(公告)日：2012-03-13

申请号：US29385928

申请日：2011-02-22

申请人： Joseph Huang

设计人： Joseph Huang

公开(公告)号：US08130016B2

公开(公告)日：2012-03-06

申请号：US12642502

申请日：2009-12-18

申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 每个可变延迟块和固定延迟块都是反相的。

公开(公告)号：US20110175657A1

公开(公告)日：2011-07-21

申请号：US12690064

申请日：2010-01-19

申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：USD640263S1

公开(公告)日：2011-06-21

申请号：US29368300

申请日：2010-08-21

申请人： Joseph Huang

设计人： Joseph Huang

公开(公告)号：US07898296B1

公开(公告)日：2011-03-01

申请号：US12624281

申请日：2009-11-23

申请人： Ning Xue ,  Philip Clarke ,  Joseph Huang ,  Yan Chong

发明人： Ning Xue ,  Philip Clarke ,  Joseph Huang ,  Yan Chong

IPC分类号： H03K19/00

CPC分类号： H03K23/54 ,  G06F1/06 ,  G06F1/10

摘要： Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

摘要翻译： 公开了用于在电子设备中分配和同步分频时钟信号的方法和电路。 在一个实施例的一个方面中，一系列寄存器分配分频时钟信号，并且该系列寄存器由全速时钟信号计时，分频时钟信号从该全速时钟信号得到。 在另一方面，分频时钟信号和全速时钟信号被分配到电子设备的IO电路。 在另一方面，分频时钟信号也分配给电子设备的核心中的电路。

公开(公告)号：US20100290181A1

公开(公告)日：2010-11-18

申请号：US12640495

申请日：2009-12-17

申请人： Joseph Huang

发明人： Joseph Huang

IPC分类号： G06F1/16

CPC分类号： H05K5/0278 ,  G06K19/077 ,  G06K19/07732

摘要： A USB flash disk is disclosed as being inserted therein with an internal structure composed of a printed circuit board, a metallic tray, a lower insulation seat and a clamping strip unit etc. for completing the USB flash disk.

摘要翻译： 公开了一种USB闪存盘，其中插入有由印刷电路板，金属托盘，下绝缘座和夹紧条单元等组成的内部结构，用于完成USB闪存盘。

公开(公告)号：US07710149B1

公开(公告)日：2010-05-04

申请号：US12190530

申请日：2008-08-12

申请人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

发明人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

IPC分类号： H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/018585

摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

摘要翻译： 输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。 例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。 一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。