公开(公告)号：US07804904B1

公开(公告)日：2010-09-28

申请号：US11089010

申请日：2005-03-24

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H03M1/0626 ,  H03M1/66 ,  H04L25/028

摘要： A communication circuit includes a near end transmitter, a hybrid having an input in communication with an output of the near end transmitter, and a near end adjustable load replication transmitter having an adjustable load. The communication circuit further includes a subtractor configured to subtract an output from the near end adjustable load replication transmitter from the output from the near end transmitter and the hybrid. The communication circuit further includes a near end receiver responsive to an output of the subtractor and a calibration circuit configured to adjust the adjustable load against a reference load.

摘要翻译： 通信电路包括近端发射机，具有与近端发射机的输出通信的输入的混合器以及具有可调载荷的近端可调载荷复制发射机。 通信电路还包括减法器，其被配置为从近端可变负载复制发射机的输出中减去来自近端发射机和混合的输出。 通信电路还包括响应于减法器的输出的近端接收器和被配置为相对于参考负载调节可调节负载的校准电路。

公开(公告)号：US07796952B1

公开(公告)日：2010-09-14

申请号：US10701626

申请日：2003-11-06

申请人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse

发明人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse

IPC分类号： H04B1/38

CPC分类号： H04B1/0064 ,  H04B7/0805

摘要： A system for communicating information signals includes a receiver in selective communication with a first antenna and a second antenna. The receiver is configured to selectively receive information signals via the first or second antenna. The system includes a first low-noise amplifier in communication with the first antenna and in selective communication with the receiver. The first low-noise amplifier is configured to amplify a first information signal received by the first antenna to generate a first amplified signal. The system includes a second low-noise amplifier in communication with the second antenna and in selective communication with the receiver. At least the first and second low-noise amplifiers are formed on a monolithic substrate. The second low-noise amplifier is configured to amplify a second information signal received by the second antenna to generate a second amplified signal. Either the first or second amplified signal is selectively applied to the receiver.

摘要翻译： 用于传送信息信号的系统包括与第一天线和第二天线选择性通信的接收机。 接收器被配置为经由第一或第二天线选择性地接收信息信号。 该系统包括与第一天线通信并与接收机选择性通信的第一低噪声放大器。 第一低噪声放大器被配置为放大由第一天线接收的第一信息信号以产生第一放大信号。 该系统包括与第二天线通信并与接收机选择性通信的第二低噪声放大器。 至少第一和第二低噪声放大器形成在单片基板上。 第二低噪声放大器被配置为放大由第二天线接收的第二信息信号以产生第二放大信号。 第一或第二放大信号被选择性地施加到接收器。

公开(公告)号：US07788514B2

公开(公告)日：2010-08-31

申请号：US12152030

申请日：2008-05-12

申请人： Sehat Sutardja ,  Hong-Yi Chen

发明人： Sehat Sutardja ,  Hong-Yi Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0897 ,  G06F13/28 ,  G06F2212/222 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode.

公开(公告)号：US07787324B2

公开(公告)日：2010-08-31

申请号：US11870833

申请日：2007-10-11

申请人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

发明人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G06F12/0877 ,  G06F12/0882 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C7/1027 ,  G11C7/12 ,  G11C11/418 ,  G11C2207/104 ,  G11C2207/2245 ,  Y02D10/13

摘要： A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.

摘要翻译： 处理器包括高速缓冲存储器。 高速缓冲存储器包括单元阵列，字线和位线。 控制模块使得字线的字线能够访问所启用的字线中的第一单元。 控制模块禁用字线并将字线保持在禁用状态，以访问字线中的第二个单元格。

公开(公告)号：US07760525B2

公开(公告)日：2010-07-20

申请号：US10693787

申请日：2003-10-24

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H02M7/48

CPC分类号： H02M3/1584 ,  H02M3/157 ,  H02M2001/0012

摘要： A regulator for converting energy from an input source to a voltage of an output. The regulator comprising at least two conduction switches to conduct energy from the input source to the output. Each of the conduction switches operated at approximately 50% duty cycle. At least two inductors in communication with the at least two conduction switches, the at least two inductors wound together on a common core and each inductor having a polarity such that DC currents in the inductors cancel each other. The inductors having a coefficient of coupling approximately greater than 0.99. At least two freewheeling switches in communication with the at least two conduction switches to provide a path for current during non-conduction periods. A drive signal generator to generate drive signals for controlling the at least two conduction switches.

摘要翻译： 用于将能量从输入源转换成输出电压的调节器。 调节器包括至少两个导通开关，以将能量从输入源传导到输出端。 每个导通开关以大约50％的占空比工作。 与所述至少两个导通开关连通的至少两个电感器，所述至少两个电感器在公共芯体上缠绕在一起，并且每个电感器具有使得所述电感器中的直流电流相互抵消的极性。 电感器的耦合系数近似大于0.99。 至少两个续流开关与至少两个导通开关连通，以在非导通时段期间为电流提供路径。 驱动信号发生器，用于产生用于控制所述至少两个导通开关的驱动信号。

公开(公告)号：US07737788B1

公开(公告)日：2010-06-15

申请号：US12004261

申请日：2007-12-20

申请人： Pierte Roo ,  Sehat Sutardja

发明人： Pierte Roo ,  Sehat Sutardja

IPC分类号： H03F3/04

CPC分类号： H03F3/265 ,  H03F1/22

摘要： A communication device includes a first polarity driver circuit including a first current source, a first amplifier that receives an input signal, that controls the first current source, and that receives a signal from the first current source, a first cascode device arranged in a cascode configuration with the first current source, and a second amplifier that receives a bias signal, that controls the first cascode device, and that receives a signal from the first cascode device.

摘要翻译： 通信装置包括第一极性驱动器电路，其包括第一电流源，接收输入信号的第一放大器，其控制第一电流源，并且接收来自第一电流源的信号;布置在共源共栅中的第一共源共栅器件 配置有第一电流源，以及第二放大器，其接收控制第一共源共用器件并从第一共源共栅器件接收信号的偏置信号。

公开(公告)号：US07737777B2

公开(公告)日：2010-06-15

申请号：US12326197

申请日：2008-12-02

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： H03F1/24

CPC分类号： H03F1/42 ,  H03F1/26 ,  H03F3/005 ,  H03F2200/18 ,  H03F2200/36

摘要： An amplifier system includes a first amplifier stage having an input and an output. A second amplifier stage has an input and an output, the input of the second amplifier stage being connected to the output of the first amplifier stage. A transistor has a control terminal, a first terminal, and a second terminal, the first terminal of the transistor being coupled to the output of the first amplifier stage and the input of the second amplifier stage. A first capacitance has a first terminal and a second terminal, the first terminal of the first capacitance being connected to the input of the first amplifier stage, the second terminal of the first capacitance being connected to the second terminal of the transistor. A first current source to source current to amplifier system, the first current source being is connected to the output of the first amplifier stage. A second current source will sink current from the amplifier system. The second current source is connected to the second terminal of the first capacitance and the second terminal of the transistor.

摘要翻译： 放大器系统包括具有输入和输出的第一放大器级。 第二放大器级具有输入和输出，第二放大级的输入端连接到第一放大级的输出。 晶体管具有控制端子，第一端子和第二端子，晶体管的第一端子耦合到第一放大器级的输出端和第二放大器级的输入端。 第一电容具有第一端子和第二端子，第一电容的第一端子连接到第一放大器级的输入端，第一电容的第二端子连接到晶体管的第二端子。 将电流源放大到放大器系统的第一电流源，第一电流源连接到第一放大器级的输出端。 第二个电流源会从放大器系统吸收电流。 第二电流源连接到第一电容的第二端子和晶体管的第二端子。

公开(公告)号：US07737666B2

公开(公告)日：2010-06-15

申请号：US10744982

申请日：2003-12-22

申请人： Sehat Sutardja ,  Jianchen Zhang ,  Sofjan Goenawan

发明人： Sehat Sutardja ,  Jianchen Zhang ,  Sofjan Goenawan

IPC分类号： G05F1/10 ,  G05F1/652

CPC分类号： H02M3/1588 ,  H02M1/32 ,  Y02B70/1466

摘要： Systems and techniques for efficient power regulators with improved reliability. A power regulator may include a first driver including a first switch and a second switch, where a power dissipation of the first switch is less than a power dissipation of the second switch. The power regulator may include a second driver. The first and second switches may be implemented as transistors, which may have different on-state breakdown voltages and/or on-state drain source resistances.

摘要翻译： 高效功率调节器的系统和技术，具有更高的可靠性。 功率调节器可以包括第一驱动器，其包括第一开关和第二开关，其中第一开关的功率损耗小于第二开关的功率耗散。 功率调节器可以包括第二驱动器。 第一和第二开关可以被实现为晶体管，其可以具有不同的导通状态击穿电压和/或导通状态漏极源极电阻。

公开(公告)号：US07730335B2

公开(公告)日：2010-06-01

申请号：US10865732

申请日：2004-06-10

申请人： Sehat Sutardja ,  Hong-Yi Chen

发明人： Sehat Sutardja ,  Hong-Yi Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0897 ,  G06F13/28 ,  G06F2212/222 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode.

摘要翻译： 用于计算机的架构包括主计算机，其以第一速率消耗功率，当计算机处于高功率模式时并且当计算机处于低功率模式时，该处理器未被供电时操作。 主要图形处理器与主处理器通信，当计算机处于高功率模式时被操作，并且当计算机处于低功率模式时不被供电。 辅助图形处理器与二级处理器进行通信。 辅助处理器以小于第一速率的第二速率消耗功率。 当计算机处于低功耗模式时，辅助处理器和辅助图形处理器被操作。

公开(公告)号：US20100127909A1

公开(公告)日：2010-05-27

申请号：US12689066

申请日：2010-01-18

申请人： Sehat Sutardja ,  Pierte Roo

发明人： Sehat Sutardja ,  Pierte Roo

IPC分类号： H03M1/12

CPC分类号： H04L25/0272 ,  H03M1/661 ,  H03M1/742 ,  H04L25/03834

摘要： A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.

摘要翻译： 电路包括T组数模转换器（DAC），每组包括N个电流源和M个延迟元件。 输出信号包括N个电流源的输出之和。 M个延迟元件中的第一个的输入和N个电流源中的第一个的控制输入接收多个解码信号中的相应的一个。 T组第一转换器各自具有反馈节点，输出和与所述T组中的相应一个DAC的输出信号通信的输入。 T第二转换器具有与T组第一转换器中的每一个的各反馈节点通信的输入。 夏天产生基于T组第一转换器的输出和T秒转换器的输出的差分信号。