公开(公告)号：US06628488B2

公开(公告)日：2003-09-30

申请号：US09874339

申请日：2001-06-06

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H02H900

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： An electrostatic discharge (ESD) protection circuit is disclosed. This invention relates an electrostatic discharge protection circuit for multi-power and mixed-voltage integrated circuit. In the electrostatic discharge protection circuit of the invention, an ESD protection cell formed with voltage selector, control circuit and transistor is used to connect with a independent power and ESD bus is used to connect with each ESD protection cell so that each power is isolated from each other during normal operation. Therefore, each power can be operated independently and circuit will be prevented from ESD during ESD discharging.

公开(公告)号：US06587387B1

公开(公告)日：2003-07-01

申请号：US10055571

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C2900

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C2029/5006

摘要： A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.

摘要翻译： 描述了面罩ROM测试装置。 掩模ROM测试装置包括衬底，衬底中的多个掩埋位线和垂直于掩埋位线的衬底上的多个字线。 每个埋置的位线具有两个具有约3〜30μm的组合长度的端部，并且可以具有N型导电性或P型导电性。

公开(公告)号：US06524913B1

公开(公告)日：2003-02-25

申请号：US10004934

申请日：2001-12-04

申请人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory, in which a charge-trapping layer consisting of insulating materials and bar-like conductive layers to be patterned into the gates are formed at first. The buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. High-K spacers are formed on the side-walls of the bar-like conductive layers. Then the bar-like conductive layers are patterned into the gates, and word-lines are formed on the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.

摘要翻译： 一种制造非易失性存储器的方法，其中首先形成由绝缘材料构成的电荷捕获层和待形成栅格的棒状导电层。 在棒状导电层之间的衬底中形成掩埋位线。 每个埋置的位线在相邻的高K间隔物的一部分下延伸到衬底中，但不延伸到相邻的棒状导电层下方的衬底。 在棒状导电层的侧壁上形成高K隔离物。 然后将棒状导电层图案化成栅极，并且在基板上形成字线以与栅极电连接。 高K间隔物的材料具有介电常数，高K间隔物具有宽度，使得沟道将在高K间隔物下延伸到衬底，并且当非挥发性的时候与掩埋位线连接 内存被操作

公开(公告)号：US06455898B1

公开(公告)日：2002-09-24

申请号：US09267303

申请日：1999-03-15

申请人： Meng-Hwang Liu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： An ESD protection structure for protecting an internal circuit comprising a primary protection device, a secondary protection device, and a substrate pickup is presented. The primary protection device and secondary protection device share a common source, and this common source implementation lowers the trigger voltage of the primary protection device to be about the same as the trigger voltage of the secondary protection device, thereby eliminating the need to use an isolation resistor between the primary and secondary protection devices.

摘要翻译： 提出了一种用于保护包括主保护装置，辅助保护装置和基板拾取器的内部电路的ESD保护结构。 主保护装置和次级保护装置共享共同的源头，这种常用的源实现将主保护装置的触发电压降低到与次级保护装置的触发电压大致相同，从而无需使用隔离 主保护和次级保护装置之间的电阻。

公开(公告)号：US06455388B1

公开(公告)日：2002-09-24

申请号：US10099802

申请日：2002-03-13

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/665

摘要： A method of fabricating a MOS transistor. First, a substrate having a gate electrode and spacers on the gate electrode sidewalls is provided. A source/drain region is formed in the substrate outside the outer edge of the spacer sidewalls. A self-aligned silicide layer is formed over the exposed surface of the gate electrode and the source/drain regions. A portion of the spacers is removed by etching to form a sharp-angled triangular spacer on the sidewalls of the gate electrode. A pocket implantation of the substrate is carried out to form a pocket region inside the substrate under the side edges of the gate electrode. By controlling the setting of the energy level and the implant angle in the pocket implantation, a precise distribution of the dopants at desired locations within the substrate is reproduced. Finally, the sharp-angled spacers are removed and then a light implantation is conducted to form source/drain extension regions in the substrate on each side of the gate electrode.

摘要翻译： 一种制造MOS晶体管的方法。 首先，提供在栅电极侧壁上具有栅电极和间隔物的基板。 源极/漏极区域形成在衬垫外侧边缘外侧的衬底中。 在栅极电极和源极/漏极区域的暴露表面上形成自对准的硅化物层。 通过蚀刻去除一部分间隔物，以在栅电极的侧壁上形成锐角三角形间隔物。 进行基板的袋式注入，以在栅电极的侧边缘下方的基板内部形成袋区域。 通过控制袋注入中的能级和植入角度的设定，再现了衬底内所需位置处的掺杂剂的精确分布。 最后，去除尖锐的间隔物，然后进行光注入以在栅电极的每一侧上的衬底中形成源极/漏极延伸区域。

公开(公告)号：US06259140B1

公开(公告)日：2001-07-10

申请号：US09410360

申请日：1999-09-30

申请人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

摘要翻译： 半导体器件形成在具有ESD区域和内部区域的衬底上。 在ESD区域的一部分上形成保护层以防止硅化物的形成，并且在保护层未保护的内部和ESD区域的部分上形成硅化物。 保护层的一部分被去除，以将保护层的剩余部分形成为与包括在ESD区域中的栅电极相邻的侧壁间隔。

公开(公告)号：US5963808A

公开(公告)日：1999-10-05

申请号：US783995

申请日：1997-01-15

申请人： Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883

摘要： A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.

摘要翻译： 具有不对称的源极和漏极连接到具有Fowler-Nordheim隧道区域的掩埋位线的存储单元以及由每个单元上的鸟喙侵入限定的非隧穿区域。 一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个位线。 一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成一列浮栅; （3）在所述浮栅的所述列的第一侧附近形成抑制掩模; （4）在所述浮栅的所述第一侧和所述第二侧附近注入掺杂剂，所述第一掺杂剂具有与所述第一导电类型相反的第二导电类型; （5）在浮置栅极列的第一和第二侧附近形成热氧化物，使得邻近该列的第一侧的掺杂剂通过电介质离开浮动栅极并且邻近该第二侧的掺杂剂是 通过鸟喙侵蚀热氧化物形成与浮动门分离; （6）完成控制栅介质和控制栅的形成。

公开(公告)号：US09153570B2

公开(公告)日：2015-10-06

申请号：US12712812

申请日：2010-02-25

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0262

摘要： An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

摘要翻译： 静电放电容纳装置包括具有第一导电类型的半导体本体和衬垫。 具有第二导电类型的周围阱布置在环中以围绕半导体本体中的静电放电电路的区域。 周围的阱相对较深，除了限定静电放电电路的区域之外，还提供了形成有半导体本体的二极管的第一端子。 在由周围的阱包围的区域内，耦合到焊盘的二极管和耦合到电压基准的晶体管串联连接并在半导体本体中形成寄生器件。

公开(公告)号：US08748936B2

公开(公告)日：2014-06-10

申请号：US13555075

申请日：2012-07-20

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域和第一阱区域内的第二导电类型的第二阱区域。 第一导电类型的第一区域和第二导电类型的第二区域设置在第二阱区域内。 第一导电类型的第三区域和第二导电类型的第四区域设置在第一阱区域内，其中第三区域和第四区域被第二阱区域分开。 半导体器件还包括耦合到第三区域的开关器件。

公开(公告)号：US20110216454A1

公开(公告)日：2011-09-08

申请号：US12719577

申请日：2010-03-08

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

IPC分类号： H02H9/04 ,  H03H11/26

CPC分类号： H02H9/04 ,  H03H11/26

摘要： An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

摘要翻译： 描述了一种用于提供静电放电（ESD）保护的RC延迟电路。 电路使用NMOS晶体管和PMOS晶体管，使用相对小的电路布局面积产生大的有效电阻。