公开(公告)号：US07749842B2

公开(公告)日：2010-07-06

申请号：US11754627

申请日：2007-05-29

申请人： Huilong Zhu ,  Steven W. Bedell ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Steven W. Bedell ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687

摘要： A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block. Accordingly, a semiconductor device having a strained Si fin vertically oriented on a non-conductive substrate may be formed where the strained Si film is oriented such that it may form a channel of small dimensions allowing access to both sides and top in order to from single gate, double gate, or more gate MOSFETs and finFETs with a channel having a reduced number of defects and/or reduced dimensions.

摘要翻译： 提供了提供具有减小的缺陷的应变Si膜的方法和装置，其中应变Si膜在非导电基板的表面上形成垂直取向的翅片。 应变Si膜或翅片可以形成具有相对较小尺寸的半导体通道，同时也具有很少的缺陷。 应变Si翅片通过在松弛的SiGe块的一侧生长Si而形成。 可以在应变Si膜的表面上形成诸如氧化物，高“k”材料或两者的组合的电介质栅极。 另外，在基本上不影响应变Si膜中的应力的情况下，可以去除弛豫的SiGe块，以允许在松弛的SiGe块先前占据的表面上形成第二栅极氧化物。 因此，可以形成具有垂直取向在非导电衬底上的应变Si鳍片的半导体器件，其中应变Si膜被定向成使得其可以形成允许接近两侧和顶部的小尺寸的通道，以便从单个 栅极，双栅极或更多栅极MOSFET和finFET，沟道具有减少的缺陷数量和/或减小的尺寸。

公开(公告)号：US07671421B2

公开(公告)日：2010-03-02

申请号：US11444011

申请日：2006-05-31

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US07666774B2

公开(公告)日：2010-02-23

申请号：US11625984

申请日：2007-01-23

申请人： Huilong Zhu ,  Dae-Gyu Park ,  Zhijiong Luo ,  Ying Zhang

发明人： Huilong Zhu ,  Dae-Gyu Park ,  Zhijiong Luo ,  Ying Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity. The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials. The second silicon containing material layer and the second semiconductor substrate region also comprise different materials.

摘要翻译： CMOS结构和制造CMOS结构的方法包括位于具有第一极性的第一半导体衬底区域内的第一晶体管。 第一晶体管包括第一栅电极，其包括第一含金属材料层和位于第一含金属材料层上的第一含硅材料层。 CMOS结构还包括位于横向分离的第二半导体衬底区域内的第二晶体管，其具有不同于第一极性的第二极性。 第二晶体管包括第二栅极电极，其包括与第一含金属材料层不同的组成的第二金属含有材料层和位于第二含金属材料层上的第二含硅材料层。 第一含硅材料层和第一半导体衬底区域包括不同的材料。 第二含硅材料层和第二半导体衬底区域也包括不同的材料。

公开(公告)号：USD598902S1

公开(公告)日：2009-08-25

申请号：US29253753

申请日：2006-02-10

申请人： Jörg Alber ,  Ying Zhang

设计人： Jörg Alber ,  Ying Zhang

公开(公告)号：US07486627B2

公开(公告)日：2009-02-03

申请号：US10453750

申请日：2003-06-03

申请人： Ying Zhang ,  Markus P. J. Fromherz ,  Sergei Vassilvitskii ,  Yi Shang

发明人： Ying Zhang ,  Markus P. J. Fromherz ,  Sergei Vassilvitskii ,  Yi Shang

IPC分类号： H04L12/28

CPC分类号： H04L45/20 ,  H04L45/121 ,  H04L45/122 ,  H04L45/44 ,  H04L47/17 ,  H04W4/24 ,  H04W28/18 ,  H04W40/08 ,  H04W40/10 ,  H04W40/12 ,  H04W40/20 ,  H04W40/26 ,  H04W48/16 ,  H04W84/18

摘要： A method is presented for a time-aware strategy utilized within message-initiated constraint-based routing for digital message communication among nodes in an ad-hoc network, in which each node includes attributes. The method includes determining local attributes for each of the nodes and defining constraints on the attributes. Each node is provided access to the attributes of each neighboring node, with a neighboring node being a node that is one hop away. Each message transmitted over the network has a message type, which includes a destination specification, route specification, and objective specification. Constraint checking and cost estimation checking are performed for each message type. The message that is routed within the network includes the address of a sending node, address of the source node, route constraints, destination constraints specified with a time bound, the number of route constraints, the number of destination constraints, message identification number, sequence identification number, and routing objectives.

摘要翻译： 提出了一种在消息发起的基于约束的路由中利用的时间感知策略的方法，用于在ad-hoc网络中的节点之间的数字消息通信，其中每个节点包括属性。 该方法包括确定每个节点的本地属性并且定义关于属性的约束。 提供每个节点对每个相邻节点的属性的访问，其中相邻节点是一跳的节点。 通过网络发送的每个消息都有一个消息类型，其中包括目的地规范，路由规范和客观规范。 对每种消息类型执行约束检查和成本估算检查。 在网络中路由的消息包括发送节点的地址，源节点的地址，路由约束，用时间限制指定的目的约束，路由约束的数量，目的约束的数量，消息标识号，序列 识别号码和路由目标。

公开(公告)号：US20080305437A1

公开(公告)日：2008-12-11

申请号：US11760992

申请日：2007-06-11

申请人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

发明人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

IPC分类号： G03C5/00

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/7833

摘要： A method for forming a patterned structure within a microelectronic structure uses a non-directly imageable organic material layer located over a substrate and a directly imageable inorganic material layer located upon the non-directly imageable organic material layer. The directly imageable inorganic material layer is directly imaged to form a patterned inorganic material layer. The patterned inorganic material layer is used as a first etch mask within a first etch method that etches the non-directly imageable organic material layer to form a patterned organic material layer. At least the patterned organic material layer is used as a second etch mask within a second etch method that etches the substrate to form a patterned structure within the substrate.

摘要翻译： 用于在微电子结构内形成图案化结构的方法使用位于基底上的非直接成像的有机材料层和位于不可直接成像的有机材料层上的可直接成像的无机材料层。 可直接成像无机材料层直接成像以形成图案化的无机材料层。 图案化的无机材料层在第一蚀刻方法中用作第一蚀刻掩模，其蚀刻非直接成像的有机材料层以形成图案化的有机材料层。 至少图案化的有机材料层在第二蚀刻方法中用作第二蚀刻掩模，其蚀刻衬底以在衬底内形成图案化结构。

公开(公告)号：US20080291024A1

公开(公告)日：2008-11-27

申请号：US11807283

申请日：2007-05-25

申请人： Ying Zhang ,  James E. Reich

发明人： Ying Zhang ,  James E. Reich

IPC分类号： G08B13/14

CPC分类号： G01S5/04 ,  G01S5/0289 ,  G01S13/876

摘要： One embodiment of the present invention provides a system that locates a set of target transmitting mechanism using a mobile sensing infrastructure. During operation, the system determines a reference frame of a sensing mechanism by detecting signals from at least two transmitting mechanisms. The system further determines locations of the target transmitting mechanism relative to the reference frame using the sensing mechanism. In addition, the system produces a result to indicate the locations of the target transmitting mechanisms.

摘要翻译： 本发明的一个实施例提供一种使用移动感测基础设施定位一组目标传送机制的系统。 在操作期间，系统通过检测来自至少两个传送机构的信号来确定感测机构的参考帧。 该系统使用感测机构进一步确定目标传送机构相对于参考系的位置。 另外，系统产生一个结果以指示目标传送机制的位置。

公开(公告)号：US20080283824A1

公开(公告)日：2008-11-20

申请号：US12173642

申请日：2008-07-15

申请人： An L. STEEGEN ,  Haining S. Yang ,  Ying Zhang

发明人： An L. STEEGEN ,  Haining S. Yang ,  Ying Zhang

IPC分类号： H01L29/778

CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

摘要翻译： 半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。 栅极堆叠在半导体衬底上。 应变层形成在至少一个间隙的至少一部分中。 应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

公开(公告)号：US20080242070A1

公开(公告)日：2008-10-02

申请号：US11694104

申请日：2007-03-30

申请人： Tze-chiang Chen ,  Bruce B. Doris ,  Rangarajan Jagannathan ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

发明人： Tze-chiang Chen ,  Bruce B. Doris ,  Rangarajan Jagannathan ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/4966 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517

摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

摘要翻译： 公开了用于制造双栅极半导体结构的多重集成方案。 通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。 对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

公开(公告)号：US07413941B2

公开(公告)日：2008-08-19

申请号：US11433806

申请日：2006-05-13

申请人： Ying Zhang ,  Bruce B. Doris ,  Thomas Safron Kanarsky ,  Meikei Ieong ,  Jakub Tadeusz Kedzierski

发明人： Ying Zhang ,  Bruce B. Doris ,  Thomas Safron Kanarsky ,  Meikei Ieong ,  Jakub Tadeusz Kedzierski

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。