公开(公告)号：US08486801B2

公开(公告)日：2013-07-16

申请号：US13297276

申请日：2011-11-16

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66545

Abstract: A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

Abstract translation: DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。 掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。 此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。 然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。 埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。

公开(公告)号：US08471320B2

公开(公告)日：2013-06-25

申请号：US13343668

申请日：2012-01-04

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L28/90

Abstract: A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.

Abstract translation: 存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

公开(公告)号：US20130062676A1

公开(公告)日：2013-03-14

申请号：US13239364

申请日：2011-09-21

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L29/40114

Abstract: A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

Abstract translation: 闪速存储器结构包括半导体衬底，半导体衬底上的栅极电介质层，栅极介电层上的浮置栅极，保形地覆盖浮置栅极的电容器电介质层，其中电容器介电层形成顶表面和四个侧壁表面 ; 以及覆盖顶表面和四个侧壁表面的隔离的导电盖层。

公开(公告)号：US08373220B1

公开(公告)日：2013-02-12

申请号：US13224561

申请日：2011-09-02

Applicant: Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

Abstract translation: 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元形成在第一电介质层上。 每个数据存储单元包括形成在第一介电层上的两个浮置栅极，分别形成在两个浮置栅极上的两个栅极间电介质层，分别形成在两个栅极间电介质层上的两个控制栅极， 第一电介质层，两个浮置栅极之间，两个栅极间电介质层之间以及两个控制栅极之间，以及形成在第一介电层上并围绕并连接两个浮动栅极的第三介质层， - 门电介质层和两个控制门。

公开(公告)号：US08283709B2

公开(公告)日：2012-10-09

申请号：US12899721

申请日：2010-10-07

Applicant: Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L29/772

CPC classification number: H01L21/76224 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

Abstract: A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

Abstract translation: 公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。 硅化物衬底具有两个掺杂区域。 氮化物层沉积在硅化物衬底上。 硅化物衬底和氮化物层具有贯穿的凹槽。 两个掺杂区位于凹槽的两侧。 凹部的端部具有比凹部大的蚀刻空间。 硅化物衬底的顶部具有鳍状结构。 两个STI位于硅化物衬底（凹槽）的两个相对侧。 应变氮化物在凹槽​​中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。 两个掺杂区域覆盖了应变氮化物。 结果，提高了半导体的效率，并且提高了驱动电流。

公开(公告)号：US08105900B2

公开(公告)日：2012-01-31

申请号：US12838495

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

Abstract translation: 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨越存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07642191B2

公开(公告)日：2010-01-05

申请号：US12019260

申请日：2008-01-24

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/823437 ,  H01L27/115 ,  H01L27/11521

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.

Abstract translation: 提供一种形成半导体结构的方法。 该方法包括提供衬底并在衬底上形成掩模层。接下来，在掩模层和衬底中形成介电隔离，其中介电隔离物延伸到衬底上方。 然后，去除掩模层以露出衬底的一部分，并且在衬底的暴露部分上形成电介质层。 随后，在电介质层上形成第一导电层，去除介电隔离的一部分，其中绝缘隔离的顶表面低于第一导电层的顶表面。 此外，在衬底上形成保形层，并且在保形层上形成第二导电层。

公开(公告)号：US20090087975A1

公开(公告)日：2009-04-02

申请号：US12018209

申请日：2008-01-23

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/3205

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US20090087544A1

公开(公告)日：2009-04-02

申请号：US12039744

申请日：2008-02-29

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: B05D5/12

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568

Abstract: The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

Abstract translation: 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

公开(公告)号：US20090065846A1

公开(公告)日：2009-03-12

申请号：US11955396

申请日：2007-12-13

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.

Abstract translation: 非易失性存储器的制造方法包括在衬底上依次形成第一电介质层，第一导电层和第一覆盖层，以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。 在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。