公开(公告)号：USRE36203E

公开(公告)日：1999-04-27

申请号：US916280

申请日：1997-08-22

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C7/1006 ,  G11C11/4096

摘要： This semiconductor circuit includes a plurality of memory cell arrays arranged mutually adjacent in one direction, a plurality of first selection/sense amplifier circuits provided in the respective regions between mutually adjacent pairs of these memory cell arrays and make access to one of alternately defined odd-numbered or even-numbered memory cell trains in the order of arrangement, two units of second selection/sense amplifier circuits arranged on the outside of the memory cell arrays on both ends of the arrangement of the plurality of memory cell arrays and make access to one of the designated odd-numbered or even-numbered memory cell trains of the memory cell arrays on both ends, a plurality of data buses corresponding to the respective bits of data transferred in bit parallel between an external circuit, and a plurality of input and output switching circuits arranged and connected in one-to-one correspondence to the respective first and second selection/sense amplifier circuits connected to the plurality of data buses so as to have an equal number of memory cell trains capable of transferring data with these data buses, and a plurality of input and output switching circuits which transfer data with the first and the second selection/sense amplifier circuits in one-to-one correspondence.

公开(公告)号：US5535163A

公开(公告)日：1996-07-09

申请号：US332727

申请日：1994-11-01

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/12 ,  G11C29/28 ,  G11C29/48 ,  G11C11/34 ,  H01L27/10

CPC分类号： G11C29/48 ,  G11C29/28

摘要： A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.

摘要翻译： 一种用于以比特为单位以并行方式输入和输出数据的多位半导体存储器件。 多位存储器具有存储单元阵列，该存储单元阵列由对应于不同IO位的混合存储器单元，分别对应于IO位的数据I / O端子，用于输入地址的地址端子和与IO位相关联的内部数据总线组成，并连接到 存储单元阵列。 此外，存储装置具有用于生成指示进入测试模式的测试模式入口信号的测试模式输入信号发生器，连接到地址终端的伪地址发生器，用于在测试模式中生成伪地址，以及 响应于测试模式输入信号的连接电路，用于根据伪地址选择一个内部数据总线，并将所选择的总线连接到预定的一个数据I / O端子。

公开(公告)号：US5369613A

公开(公告)日：1994-11-29

申请号：US709946

申请日：1991-06-04

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C7/10 ,  G11C7/02 ,  G11C11/40

CPC分类号： G11C7/1048

摘要： The semiconductor memory device according to the present invention includes a memory cell array consisting of a plurality memory cells provided in array form and a plurality of bit lines and word lines connected respectively to the plurality of memory cells, I/O lines consisting of a first wiring and a second wiring connected to a predetermined number of bit lines out of the plurality of the bit lines via a selection circuit, and a clamping circuit which is activated at the time of read and includes a first device which connects the first wiring and the second wiring when the potential of the first wiring exceeds the potential of the second wiring by more than a predetermined voltage value, and a second device which connects the first wiring and the second wiring when the potential of the second wiring exceeds the potential of the first wiring by more than the predetermined voltage. Thus, even when a potential drop is generated in the I/O lines during the transition period, a marked drop in the potential of one of the wirings can be prevented by the clamping operation between the two wirings that constitute the I/O lines. Accordingly, it is possible to prevent the destruction of data in the memory cells, and to enhance the reading speed of the next data because of the small value of the potential drop of the wiring.

摘要翻译： 根据本发明的半导体存储器件包括由阵列形式提供的多个存储单元和分别连接到多个存储单元的多个位线和字线组成的存储单元阵列，由第一 布线和经由选择电路连接到多个位线中的预定数量的位线的第二布线，以及在读取时被激活的钳位电路，并且包括将第一布线和 当第一布线的电位超过第二布线的电位超过预定电压值时的第二布线;以及当第二布线的电位超过第一布线的电位时，连接第一布线和第二布线的第二布线 接线超过预定电压。 因此，即使在过渡期间在I / O线中产生电位降，也可以通过构成I / O线的两条配线之间的夹紧动作来防止其中一条配线的电位明显下降。 因此，可以防止存储单元中的数据的破坏，并且由于布线的电位降的较小值而提高下一数据的读取速度。

公开(公告)号：US5353375A

公开(公告)日：1994-10-04

申请号：US922179

申请日：1992-07-30

申请人： Michiyo Goto ,  Yoshinori Matsui

发明人： Michiyo Goto ,  Yoshinori Matsui

IPC分类号： H04B1/66 ,  G10L9/00

CPC分类号： H04B1/665

摘要： Disclosed is an invention concerning a quantization bit number allocating section for sub-band coding, wherein data important for human auditory sense are efficiently coded within a limited coding bit capacity to provide a high-quality digital audio signal. The quantization bit number allocating section comprises a level calculating section, a logarithm calculating section, an index calculating section, a quantization bit number calculating section, a logarithm weighting table, and a sub-band weighting table, wherein the quantization bit number is determined every prescribed time according to human auditory sense and the characteristic of an input digital audio signal.

摘要翻译： 公开了涉及用于子带编码的量化比特数分配部分的发明，其中对于人类听觉重要的数据在有限的编码比特容量内被有效地编码以提供高质量的数字音频信号。 量化位数分配部分包括电平计算部分，对数计算部分，索引计算部分，量化位数计算部分，对数加权表和子带加权表，其中每个 根据人的听觉和输入数字音频信号的特性规定时间。

公开(公告)号：US08675422B2

公开(公告)日：2014-03-18

申请号：US13204276

申请日：2011-08-05

申请人： Kiyohiro Furutani ,  Yoshinori Matsui

发明人： Kiyohiro Furutani ,  Yoshinori Matsui

IPC分类号： G11C7/06

CPC分类号： G11C11/4074 ,  G11C5/147

摘要： A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.

摘要翻译： 半导体器件包括内部电路和内部电压产生电路，其产生相对于从外部提供的电源电压的变化而稳定的内部电压并将内部电压提供给内部电路。 内部电压产生电路执行控制，使得当电源电压上升到超过预定值时，停止内部电压稳定的操作，以使内部电压随着电源电压的上升而增加。

公开(公告)号：US08598931B2

公开(公告)日：2013-12-03

申请号：US13208976

申请日：2011-08-12

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： H03H11/26

CPC分类号： H03K5/04 ,  G11C7/04 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H03K5/133 ,  H03K5/153

摘要： To cancel a delay time that occurs in a delay circuit due to temperature and voltage changes. The delay circuit includes a plurality of first and second inverters that are each composed of an N-channel first transistor and a P-channel second transistor connected in series, and P-channel third transistors that are connected between a first power supply wiring and the input nodes of the second inverters. According to the present invention, the presence of the third transistors cancels characteristic variations of the second transistors included in the respective plurality of inverters even if there are changes in temperature, voltage, etc. Consequently, when temperature, voltage, or the like changes, variations in the amount of delay of the entire delay circuit can be regarded as resulting from characteristic variations of the first transistors.

摘要翻译： 取消由于温度和电压变化引起的延迟电路中的延迟时间。 延迟电路包括多个第一和第二反相器，它们分别由串联连接的N沟道第一晶体管和P沟道第二晶体管构成，P沟道第三晶体管连接在第一电源布线和第 第二个逆变器的输入节点。 根据本发明，即使存在温度，电压等变化，第三晶体管的存在也抵消了包括在多个逆变器中的第二晶体管的特性变化。因此，当温度，电压等发生变化时， 整个延迟电路的延迟量的变化可以被认为是由第一晶体管的特性变化引起的。

公开(公告)号：US20130138903A1

公开(公告)日：2013-05-30

申请号：US13387815

申请日：2011-11-25

申请人： Yoshinori Matsui ,  Masami Kameda

发明人： Yoshinori Matsui ,  Masami Kameda

IPC分类号： G06F12/16

CPC分类号： G06F3/0605 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067

摘要： In an aspect of the invention, a primary storage system (P system) manages write times of write data of one or more primary volumes (P volumes). The P system sequentially sends journals including write data of the P volumes and values indicating order of writing the write data of the P volumes to the secondary storage system (S system). The S system sequentially stores the write data in the journals from the P system to one or more secondary volumes (S volumes) according to the values. The S system sends identification information on the latest write data of the S volumes to the P system. The P system sends a management system information to indicate the latency between the write time of the data identified with the identification information and the write time of the latest data of the P volumes at the time of receipt of the identification information.

摘要翻译： 在本发明的一个方面，主存储系统（P系统）管理一个或多个主卷（P卷）的写入数据的写入时间。 P系统顺序地发送包括P卷的写入数据和表示将P卷的写入数据写入次级存储系统（S系统）的值的值的期刊。 S系统根据这些值将写入数据顺序地存储在从P系统到一个或多个辅助卷（S卷）的期刊中。 S系统将S卷的最新写入数据的识别信息发送给P系统。 P系统发送管理系统信息，以指示识别信息识别的数据的写入时间与接收到识别信息时的P卷的最新数据的写入时间之间的等待时间。

公开(公告)号：US08375240B2

公开(公告)日：2013-02-12

申请号：US12270546

申请日：2008-11-13

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G06F1/00

CPC分类号： G11C7/1048 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C8/18 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/028 ,  G11C29/50012

摘要： A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

摘要翻译： 可以通过减少由存储器控制器和存储器模块之间的各种布线中的分支和阻抗失配引起的反射信号等的影响以及由于数据的传输延迟，命令的影响而实现高速操作的存储系统 /地址和内存模块中的时钟。 为此，存储器系统包括存储器控制器和安装有DRAM的存储器模块。 缓冲区安装在内存模块上。 缓冲器和存储器控制器通过数据接线，命令/地址接线和时钟接线相互连接。 存储器模块中的DRAM和缓冲器通过内部数据接线，内部命令/地址布线和内部旋塞线连接。 数据接线，命令/地址接线和时钟接线可以级联连接到其他存储器模块的缓冲器。 在DRAM和存储器模块的缓冲器之间，使用与时钟同步的数据相位信号实现高速数据传输。

公开(公告)号：US08310897B2

公开(公告)日：2012-11-13

申请号：US13067849

申请日：2011-06-29

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C8/00

CPC分类号： G11C7/1075

摘要： A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder.

摘要翻译： 一种半导体器件，包括第一存储单元阵列，第二存储单元阵列，命令解码器，被配置为产生将存储在第一存储单元阵列的第一区域中的数据传送到第二存储单元的第二区域的传送命令 阵列，当接收到第一存储单元阵列的读取命令并且顺序地向第二单元存储器阵列写入命令时，第一地址生成器被配置为产生用于指定第一存储单元阵列的第一区域的第一内部地址， 命令解码器传输命令; 以及第二地址发生器，被配置为当从命令解码器接收到传送命令时，产生用于指定第二存储单元阵列的第二区域的第二内部地址。

公开(公告)号：US08041911B2

公开(公告)日：2011-10-18

申请号：US12132266

申请日：2008-06-03

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G06F13/00

CPC分类号： G06F11/2064 ,  G06F11/2074

摘要： A remote copy system comprises a primary storage system having a primary volume, and a secondary storage system having a secondary volume forming a pair relationship with the primary volume. When the primary storage system receives a write command from a primary host computer, it stores the command in the primary volume and creates a journal added with time information. The secondary storage system receives the journal from the primary storage system and updates the secondary volume based on the received journal. The primary host computer determines, based on the operating status of the secondary storage system, either the time added to the latest journal that the secondary storage system received or the time added to the latest journal that updated the secondary volume as the recovery point objective, and provides the determined time this to the user.

摘要翻译： 远程复制系统包括具有主卷的主存储系统和具有与主卷形成对对关系的辅助卷的辅助存储系统。 当主存储系统从主主机接收写入命令时，它将该命令存储在主卷中，并创建添加了时间信息的日志。 辅助存储系统从主存储系统接收日志，并根据收到的日志更新次要卷。 主主机基于辅助存储系统的操作状态，确定辅助存储系统接收到的最新日志所添加的时间或添加到更新辅助卷的最新日志的时间作为恢复点目标， 并将确定的时间提供给用户。