公开(公告)号：US20080085579A1

公开(公告)日：2008-04-10

申请号：US11896883

申请日：2007-09-06

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

摘要翻译： 具有高电压维持能力的半导体结构。 具有高电压维持能力的半导体结构包括第一导电类型的第一阱区域。 与第一导电类型相反的第二导电类型的一对第二阱区分别设置为与第一阱区相邻，并且第一导电类型的抗穿通区域设置在至少第一阱的下部 区域以增加其中的掺杂浓度。 由于抗穿透区域的离子补充，可以进一步降低半导体结构的尺寸而不影响HV维持能力，并且可以防止诸如穿透效果等不期望的影响。

公开(公告)号：US07279767B2

公开(公告)日：2007-10-09

申请号：US11048914

申请日：2005-02-03

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L23/58

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

摘要翻译： 具有高电压维持能力的半导体结构。 具有高电压维持能力的半导体结构包括第一导电类型的第一阱区域。 与第一导电类型相反的第二导电类型的一对第二阱区分别设置为与第一阱区相邻，并且第一导电类型的抗穿通区域设置在至少第一阱的下部 区域以增加其中的掺杂浓度。 由于抗穿透区域的离子补充，可以进一步降低半导体结构的尺寸而不影响HV维持能力，并且可以防止诸如穿透效果等不期望的影响。

公开(公告)号：US20060286735A1

公开(公告)日：2006-12-21

申请号：US11505957

申请日：2006-08-17

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US20060170060A1

公开(公告)日：2006-08-03

申请号：US11048914

申请日：2005-02-03

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

公开(公告)号：US5858854A

公开(公告)日：1999-01-12

申请号：US730382

申请日：1996-10-16

申请人： Chao-Chieh Tsai ,  Shun-Liang Hsu ,  Tsu Shih

发明人： Chao-Chieh Tsai ,  Shun-Liang Hsu ,  Tsu Shih

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method of forming high contrast alignment marks on an integrated circuit wafer for patterning a layer of highly reflective electrode metal is described. A method of patterning a layer of highly reflective metal on an integrated circuit wafer using high contrast alignment marks is also described. Due to a difference in height of alignment marks and contact metal surrounding the alignment marks the alignment marks are transferred to the contour of the highly reflective electrode metal. A non reflective layer of bottom anti-reflection coating material is then used to provide high contrast at the location where the edges of the alignment marks are transferred to the highly reflective electrode metal.

摘要翻译： 描述了在用于图案化高反射电极金属层的集成电路晶片上形成高对比度对准标记的方法。 还描述了使用高对比度对准标记在集成电路晶片上图案化高反射金属层的方法。 由于对准标记的高度差和对准标记周围的接触金属的差异，对准标记被转印到高反射电极金属的轮廓上。 然后使用底部防反射涂层材料的非反射层来在对准标记的边缘被转印到高反射电极金属的位置处提供高对比度。

公开(公告)号：US5641710A

公开(公告)日：1997-06-24

申请号：US661243

申请日：1996-06-10

申请人： Jyh-Haur Wang ,  Shun-Liang Hsu

发明人： Jyh-Haur Wang ,  Shun-Liang Hsu

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

摘要： A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that created an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

摘要翻译： 已经开发了一种在小直径接触孔中铝基互连结构覆盖钨插塞结构的方法。 通过使用含卤素的蚀刻剂从接触孔以外的区域除去不想要的钨，并且使用在钨插塞的中心产生不想要的缝隙的RIE过蚀刻循环，从而形成钨插塞。 在氮环境中的后RIE退火从周围的介电层去除水分，并且还形成保护性的含氮钨层，填充钨塞的缝隙。 缝隙的填充允许获得平面覆盖的铝基互连结构。

公开(公告)号：US5510637A

公开(公告)日：1996-04-23

申请号：US387433

申请日：1995-02-13

申请人： Shun-Liang Hsu ,  Mou-Shiung Lin ,  Ming-Dar Lei

发明人： Shun-Liang Hsu ,  Mou-Shiung Lin ,  Ming-Dar Lei

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L27/0629

摘要： A method of forming a polycide-to-polysilicon capacitor with a low voltage coefficient and high linearity is described. A a first layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the substrate and the field oxide regions. A layer of silicide is deposited over the polysilicon layer. The layer of silicide and the layer of polysilicon on the field oxide region are patterned, to form a polycide bottom plate of the capacitor. The polycide bottom plate is annealed. Sidewalls are formed on the sides of the polycide bottom plate. The polycide bottom plate is ion implanted in a vertical to produce the low voltage coefficient and high linearity. An interpoly dielectric layer is formed and patterned on the surface of the polycide bottom plate to act as a dielectric for the polycide-to-polysilicon capacitor. The interpoly dielectric layer is densified. A second layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the dielectric layer and on the surface of the substrate and the field oxide regions. The second layer of polysilicon is patterned to form the top plate of the capacitor.

公开(公告)号：US5451529A

公开(公告)日：1995-09-19

申请号：US270764

申请日：1994-07-05

申请人： Shun-Liang Hsu ,  Chun-Yi Shih

发明人： Shun-Liang Hsu ,  Chun-Yi Shih

IPC分类号： H01L21/66 ,  H01L23/544 ,  H01L21/00

CPC分类号： H01L22/26 ,  H01L22/34 ,  Y10S148/083 ,  Y10S148/162

摘要： A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.

摘要翻译： 已经发明了用于实时监测离子注入剂量的新技术。 这是第一个覆盖高剂量范围（10E13至10E16离子/平方厘米）的实时显示器。 这种新技术的基本原理是离子注入后金属硅化物膜的电阻增加。 已经包括在标准生产晶片中的硅化物膜的这种增加的测量提供了与植入离子剂量相关的指标。

公开(公告)号：US07122876B2

公开(公告)日：2006-10-17

申请号：US10916133

申请日：2004-08-11

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L29/00

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US20060113640A1

公开(公告)日：2006-06-01

申请号：US10998423

申请日：2004-11-29

申请人： Hsiu-Mei Yu ,  Ken-Shen Chou ,  Shun-Liang Hsu

发明人： Hsiu-Mei Yu ,  Ken-Shen Chou ,  Shun-Liang Hsu

IPC分类号： H01L23/58

CPC分类号： H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

摘要： In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.

摘要翻译： 在一个实施方案中，本公开涉及通过注入表面回收聚合物绝缘层的方法和装置。 该方法包括提供其上具有导电焊盘和绝缘层的衬底，任选地处理导电焊盘以去除形成在导电焊盘上的氧化物层并导电离子注入以恢复绝缘层的介电性能。