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    Post tungsten etch bank anneal, to improve aluminum step coverage
    1.
    发明授权
    Post tungsten etch bank anneal, to improve aluminum step coverage 失效
    后钨蚀刻库退火，以提高铝台阶覆盖

    公开(公告)号：US5866947A

    公开(公告)日：1999-02-02

    申请号：US822247

    申请日：1997-03-20

    申请人： Jyh-Haur Wang ,  Shun-Liang Hsu

    发明人： Jyh-Haur Wang ,  Shun-Liang Hsu

    IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

    摘要： A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that creates an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

    摘要翻译： 已经开发了一种在小直径接触孔中铝基互连结构覆盖钨插塞结构的方法。 通过使用含卤素的蚀刻剂从接触孔以外的区域除去不想要的钨，并且使用在钨插塞的中心产生不想要的缝隙的RIE过蚀刻循环，来形成钨插塞。 在氮环境中的后RIE退火从周围的介电层去除水分，并且还形成保护性的含氮钨层，填充钨塞的缝隙。 缝隙的填充允许获得平面覆盖的铝基互连结构。

    Post tungsten etch back anneal, to improve aluminum step coverage
    2.
    发明授权
    Post tungsten etch back anneal, to improve aluminum step coverage 失效
    钨后退退火，以提高铝步骤覆盖

    公开(公告)号：US5641710A

    公开(公告)日：1997-06-24

    申请号：US661243

    申请日：1996-06-10

    申请人： Jyh-Haur Wang ,  Shun-Liang Hsu

    发明人： Jyh-Haur Wang ,  Shun-Liang Hsu

    IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/28

    CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

    摘要： A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that created an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

    摘要翻译： 已经开发了一种在小直径接触孔中铝基互连结构覆盖钨插塞结构的方法。 通过使用含卤素的蚀刻剂从接触孔以外的区域除去不想要的钨，并且使用在钨插塞的中心产生不想要的缝隙的RIE过蚀刻循环，从而形成钨插塞。 在氮环境中的后RIE退火从周围的介电层去除水分，并且还形成保护性的含氮钨层，填充钨塞的缝隙。 缝隙的填充允许获得平面覆盖的铝基互连结构。

    Method of improving the voltage coefficient of resistance of high polysilicon resistors
    5.
    发明授权
    Method of improving the voltage coefficient of resistance of high polysilicon resistors 有权
    提高高多晶硅电阻电阻电压系数的方法

    公开(公告)号：US06291306B1

    公开(公告)日：2001-09-18

    申请号：US09357243

    申请日：1999-07-19

    申请人： Yung-Lung Hsu ,  Shun-Liang Hsu ,  Yean-Kuen Fang ,  Mao-Hsiung Kuo

    发明人： Yung-Lung Hsu ,  Shun-Liang Hsu ,  Yean-Kuen Fang ,  Mao-Hsiung Kuo

    IPC分类号： H01L2120

    CPC分类号： H01L28/20 ,  H01L27/0802

    摘要： A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.

    摘要翻译： 一种在电介质层上形成高多晶硅电阻的方法，包括以下步骤。 提供了半导体结构上的多晶硅电阻器。 多晶硅电阻器具有掺杂多晶硅层，其具有第一电压电阻系数和具有第一捕获密度的晶界。 通过掺杂多晶硅层将A到第一级DC电流提供预定持续时间，以施加掺杂多晶硅层以部分地熔化掺杂多晶硅层而不引起掺杂多晶硅层的击穿。 除去第一级直流电流以允许熔融掺杂多晶硅层重结晶，由此再结晶掺杂多晶硅层具有小于第一电压系数电阻的第二电压系数和具有第二陷阱密度的晶界， 小于第一个捕获密度。 这使得多晶硅的Rs稳定和饱和。

    LOCOS field oxide and field oxide process using silicon nitride spacers
    6.
    发明授权
    LOCOS field oxide and field oxide process using silicon nitride spacers 失效
    使用氮化硅间隔物的LOCOS场氧化物和场氧化物工艺

    公开(公告)号：US5895257A

    公开(公告)日：1999-04-20

    申请号：US691288

    申请日：1996-08-01

    申请人： Chaochieh Tsai ,  Yuan-Chang Huang ,  Juing-Yi Wu ,  Shun-Liang Hsu

    发明人： Chaochieh Tsai ,  Yuan-Chang Huang ,  Juing-Yi Wu ,  Shun-Liang Hsu

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202

    摘要： A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are formed in the field oxide which result in poor step coverage during successive process steps. Nitride spacers are formed on the sidewalls of the field oxide covering the recesses. The spacers provide a smooth surface over the field oxide and improved step coverage during subsequent process steps.

    摘要翻译： 场氧化物区域和使用LOCOS工艺形成场氧化物区域的方法和形成在场氧化物区域的侧壁上的氮化物间隔物。 在LOCOS过程中，在场氧化物中形成凹陷，这在连续的工艺步骤期间导致差的台阶覆盖。 氮化物间隔物形成在覆盖凹部的场氧化物的侧壁上。 间隔物在场氧化物上提供光滑的表面，并在随后的工艺步骤中改善了台阶覆盖。

    MOS device structure and integration method
    7.
    发明授权
    MOS device structure and integration method 失效
    MOS器件结构和集成方法

    公开(公告)号：US5691212A

    公开(公告)日：1997-11-25

    申请号：US721665

    申请日：1996-09-27

    申请人： Chaochieh Tsai ,  Shun-Liang Hsu

    发明人： Chaochieh Tsai ,  Shun-Liang Hsu

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/265

    CPC分类号： H01L29/66575 ,  H01L21/76895 ,  H01L29/41783 ,  Y10S438/92 ,  Y10S438/966

    摘要： This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600.degree. C. in nitrogen converts the deposited silicon layer into elevated source and drains. A refractory metal, such as titanium is then deposited over the substrate and, upon rapid thermal annealing, reacts with the elevated source and drain polysilicon to form silicide without consuming the substrate silicon, and without ill effect on the source/drain junctions in the single crystalline silicon. The chance of silicide bridging is greatly reduced due to the special geometry of the novel sidewall oxide spacers.

    摘要翻译： 本发明描述了一种用于形成用于MOSFET中的自对准硅化物的新方法，以及具有升高的源极和漏极的MOSFET器件的新结构，其目的是减少硅化物穿入到源极和漏极结中以消除结尖峰 在硅化物和硅衬底之间获得更平滑的界面，并且减少栅极和源极和漏极上的硅化物桥接的机会。 通过在栅极侧壁上已经用场氧化物，栅极氧化物，多晶硅栅极和氮化硅间隔物图案化的硅衬底上沉积硅非晶层来制造新结构。 然后通过首先将氮注入到非晶硅层的水平表面中并随后在不暴露于氮注入的垂直侧壁上热氧化非晶硅的一部分来创建新的氧化物侧壁间隔物。 随后在氮气中在600℃退火的掺杂剂注入将沉积的硅层转化为升高的源和排水。 然后将难熔金属（例如钛）沉积在衬底上，并且在快速热退火时，与升高的源极和漏极多晶硅反应形成硅化物，而不消耗衬底硅，并且对单个源极/漏极结没有不利影响 晶体硅。 由于新型侧壁氧化物间隔物的特殊几何形状，硅化物桥接的机会大大降低。

    Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers
    8.
    发明授权
    Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers 失效
    使用薄壁侧壁间隔物制造NMOS和PMOS LDD晶体管的方法

    公开(公告)号：US5460993A

    公开(公告)日：1995-10-24

    申请号：US415321

    申请日：1995-04-03

    申请人： Shun-Liang Hsu ,  Shyh-Chyi Wong

    发明人： Shun-Liang Hsu ,  Shyh-Chyi Wong

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/8232 ,  H01L21/8234

    CPC分类号： H01L21/823864 ,  H01L27/0922

    摘要： A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit is described. A semiconductor substrate is provided wherein NMOS and PMOS regions are separated by an isolation region. Gate electrodes are formed in the NMOS and PMOS regions. Lightly doped regions are implanted into the semiconductor substrate within the NMOS and PMOS regions. A spacer material layer is deposited over the gate electrodes in the NMOS and PMOS regions and etched away to leave spacers on the sidewalls of the gate electrodes. The NMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the PMOS region. The photoresist mask is removed. After the PMOS implantation, a portion of the spacers is etched away to leave narrower spacers on the sidewalls of the gate electrodes. The PMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the NMOS region. The photoresist mask is removed and the fabrication of the integrated circuit is completed.

    摘要翻译： 描述了在集成电路的制造中形成用于NMOS和PMOS的不同宽度间隔物的方法。 提供了半导体衬底，其中NMOS和PMOS区被隔离区隔开。 在NMOS和PMOS区域中形成栅电极。 轻掺杂区域注入到NMOS和PMOS区域内的半导体衬底中。 间隔材料层沉积在NMOS和PMOS区域中的栅电极上，并被蚀刻掉以在栅电极的侧壁上留下间隔物。 NMOS区域被光阻掩模覆盖。 将重掺杂的源极和漏极区域注入到PMOS区域内的半导体衬底中。 去除光致抗蚀剂掩模。 在PMOS注入之后，间隔物的一部分被蚀刻掉以在栅电极的侧壁上留下较窄的间隔物。 PMOS区域被光阻掩模覆盖。 将重掺杂的源极和漏极区域注入到NMOS区域内的半导体衬底中。 去除光致抗蚀剂掩模并完成集成电路的制造。

    Method for fabrication of w-polycide-to-poly capacitors with high linearity
    9.
    发明授权
    Method for fabrication of w-polycide-to-poly capacitors with high linearity 失效
    制造高线性的多晶硅 - 多晶硅电容器的方法

    公开(公告)号：US5338701A

    公开(公告)日：1994-08-16

    申请号：US145154

    申请日：1993-11-03

    申请人： Shun-Liang Hsu ,  Chun-Yi Shi ,  Mou-Shiung Lin

    发明人： Shun-Liang Hsu ,  Chun-Yi Shi ,  Mou-Shiung Lin

    IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L21/283

    CPC分类号： H01L28/40

    摘要： A method of forming a polycide-to-polysilicon capacitor simultaneously with a CMOS device with polycide gate is described. Field oxide regions, n-well and p-well regions, and gate oxide regions are formed in and on a silicon substrate. A first layer of polysilicon, having a suitable doping concentration, is formed on the surface of the substrate and the field oxide regions. A layer of silicide is formed over the layer of polysilicon. The layer of silicide is ion implanted in a vertical direction to produce the low voltage coefficient and high linearity. A layer of interpoly oxide is formed over the layer of silicide. The layer of interpoly oxide is densified. A second layer of polysilicon is formed on the surface of the interpoly oxide. The second layer of polysilicon is doped, and then patterned to form the top plate of the capacitor. The layer of interpoly oxide is removed, except in the area under the top plate of the capacitor, where it acts as a capacitor dielectric. The layer of silicide and the layer of polysilicon are patterned to form a polycide bottom plate of the capacitor and to form the polycide gate. The layer of silicide is annealed. The source and drain regions of the CMOS device are formed in the substrate in the regions between the polycide gate and the field oxide regions; and the remaining layers are formed to complete the integrated circuit.

    摘要翻译： 描述了与具有多晶硅栅极的CMOS器件同时形成多晶硅多晶硅电容器的方法。 在硅衬底上形成场氧化物区域，n阱和p阱区域以及栅极氧化物区域。 在衬底和场氧化物区域的表面上形成具有合适掺杂浓度的第一多晶硅层。 在多晶硅层上形成一层硅化物。 硅化物层沿垂直方向离子注入，产生低电压系数和高线性度。 在硅化物层上形成一层多层氧化物。 层间氧化物层被致密化。 在多晶硅的表面上形成第二层多晶硅。 第二层多晶硅被掺杂，然后被图案化以形成电容器的顶板。 去除层间氧化物层，除了在电容器的顶板下方的区域中，其用作电容器电介质。 将硅化物层和多晶硅层图案化以形成电容器的多晶硅底板并形成多晶硅栅极。 硅化物层退火。 CMOS器件的源极和漏极区域在多晶硅栅极和场氧化物区域之间的区域中形成在衬底中; 并且形成剩余的层以完成集成电路。

    Lateral power MOSFET with high breakdown voltage and low on-resistance
    10.
    发明授权
    Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
    具有高击穿电压和低导通电阻的侧向功率MOSFET

    公开(公告)号：US08129783B2

    公开(公告)日：2012-03-06

    申请号：US12329285

    申请日：2008-12-05

    申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

    发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

    摘要翻译： 提供具有高击穿电压和低导通电阻的半导体器件。 一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。 在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。 场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。 晶体管的源极和漏极区位于高压P阱和高压N阱中。 可选地，在场电介质下的N阱区域中形成P场环。 在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。