公开(公告)号：US08809184B2

公开(公告)日：2014-08-19

申请号：US13465633

申请日：2012-05-07

申请人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

发明人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/441 ,  H01L23/535

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

摘要翻译： 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。

公开(公告)号：US08735050B2

公开(公告)日：2014-05-27

申请号：US13567233

申请日：2012-08-06

申请人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

发明人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G03F7/70466 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 一种方法包括创建包括第一和第二相邻单元格的主图案布局。 第一相邻单元具有带有第一路由线的第一边界引脚。 第二相邻单元具有带有第二路由线的第二边界引脚。 第一和第二路由线重叠以限定边缘线迹以耦合第一和第二边界引脚。 主模式布局被分解为子模式。

公开(公告)号：US08719757B2

公开(公告)日：2014-05-06

申请号：US13603304

申请日：2012-09-04

申请人： Lei Yuan ,  Jongwook Kye

发明人： Lei Yuan ,  Jongwook Kye

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.

摘要翻译： 公开了一种使用DPT实现电路设计中的点动功能的方法，而不需要难以实现诸如针迹感知路由工具的工具。 实施例包括：显示用于生成具有用于单层的多个掩模的IC的用户界面; 至少部分地使得包括填充单元的IC的单元放置的用户界面中的呈现; 并且将所述填充单元的一部分指定为路由区域，所述路由区域被配置为使得放置在所述路由区域中的路由可以与放置在所述填充单元之外的其他路由分解。

公开(公告)号：US20140097892A1

公开(公告)日：2014-04-10

申请号：US13646760

申请日：2012-10-08

申请人： Lei Yuan ,  Jongwook Kye ,  Mahbub Rashed ,  Qinglei Wang

发明人： Lei Yuan ,  Jongwook Kye ,  Mahbub Rashed ,  Qinglei Wang

IPC分类号： G06F17/50 ,  H01L25/00

CPC分类号： G06F17/5077 ,  H01L25/00 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

摘要翻译： 公开了一种利用无色DPT M1路由放置的电路设计中的功能的方法，其保持高路由效率并保证目标模式和所得电路的M1可分解性。 实施例包括：确定与IC中的第一和第二小区邻接的边界; 确定所述第一单元中面向所述第二单元中的第二边缘销的一侧的第一边缘销的一侧; 确定第一边缘销的侧面的至少一部分的第一垂直段和第二边缘销的侧面的至少一部分的第二垂直段; 指定所述第一垂直段和所述边界之间的区域作为路由区的第一部分; 并且指定所述第二垂直段和所述边界之间的区域作为所述路由区的第二部分。

公开(公告)号：US20140077384A1

公开(公告)日：2014-03-20

申请号：US13617952

申请日：2012-09-14

申请人： Juhan Kim ,  Jongwook Kye

发明人： Juhan Kim ,  Jongwook Kye

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.

摘要翻译： 公开了一种用于提供具有三层图案化金属层结构的位单元的方法。 实施例包括：通过金属层的第一图案化工艺提供作为字线结构，接地线结构，电力线结构和位线结构中的第一个的第一结构; 通过所述金属层的第二图案化处理提供与所述第一结构不同的第二结构，并且所述第二结构是所述字线结构，所述接地线结构，所述电力线结构和所述位线结构中的第二结构。 并且经由所述金属层的第三图案化处理提供与所述第一结构和所述第二结构不同的第三结构，并且所述第三结构是所述字线结构，所述接地线结构线，所述电力线结构 ，和位线结构。

公开(公告)号：US07855048B1

公开(公告)日：2010-12-21

申请号：US10838704

申请日：2004-05-04

申请人： Cyrus E. Tabery ,  Bruno M. LaFontaine ,  Adam R. Pawloski ,  Jongwook Kye

发明人： Cyrus E. Tabery ,  Bruno M. LaFontaine ,  Adam R. Pawloski ,  Jongwook Kye

IPC分类号： G02F1/01

CPC分类号： G03F7/091 ,  G03F7/70958

摘要： A method of fabricating a semiconductor device using lithography. The method can include providing a wafer assembly having a layer to be processed disposed under a photo resist layer and illuminating the wafer assembly with an exposure dose transmitted through a birefringent material disposed between a final optical element of an imaging subsystem used to transmit the exposure dose and the photo resist layer. Also disclosed is a wafer assembly from which at least one semiconductor device can be fabricated. The wafer assembly can include a layer to be processed, a photo resist layer disposed over the layer to be processed and a contrast enhancing, birefringent top anti-reflecting coating (TARC).

摘要翻译： 使用光刻制造半导体器件的方法。 该方法可以包括提供具有待处理层的晶片组件，其设置在光致抗蚀剂层下方并且以透射通过双折射材料的曝光剂量照射晶片组件，所述双折射材料设置在用于透射曝光剂量的成像子系统的最终光学元件之间 和光刻胶层。 还公开了可以制造至少一个半导体器件的晶片组件。 晶片组件可以包括待处理的层，设置在待处理层上的光致抗蚀剂层和增强对比度的双折射顶部抗反射涂层（TARC）。

公开(公告)号：US20080292991A1

公开(公告)日：2008-11-27

申请号：US11753443

申请日：2007-05-24

申请人： Thomas I. Wallow ,  Ryoung-Han Kim ,  Jongwook Kye

发明人： Thomas I. Wallow ,  Ryoung-Han Kim ,  Jongwook Kye

IPC分类号： G03C5/00 ,  H01L21/31

CPC分类号： G03F7/0035 ,  G03F7/168 ,  H01L21/0273 ,  H01L21/3086

摘要： An integrated circuit fabrication process as described herein employs a double photoresist exposure technique. After creation of a first pattern of photoresist features on a wafer, a second photoresist layer is formed over the first pattern of photoresist features. The second photoresist layer is subjected to a reflow step that softens and relaxes the second photoresist material. This reflow step causes the exposed surface of the second photoresist layer to become substantially planar. Thereafter, the second photoresist layer can be exposed and developed to create a second pattern of photoresist features on the wafer. The planar surface of the second photoresist layer, which results from the reflow step, facilitates the creation of accurate, precise, and “high fidelity” photoresist features from the second photoresist material.

摘要翻译： 本文所述的集成电路制造工艺采用双光致抗蚀剂曝光技术。 在晶片上形成光致抗蚀剂特征的第一图案之后，在光致抗蚀剂特征的第一图案之上形成第二光致抗蚀剂层。 对第二光致抗蚀剂层进行软化和松弛第二光致抗蚀剂材料的回流步骤。 该回流步骤使得第二光致抗蚀剂层的暴露表面变得基本上平坦。 此后，可以对第二光致抗蚀剂层进行曝光和显影以在晶片上产生光致抗蚀剂特征的第二图案。 由回流步骤产生的第二光致抗蚀剂层的平坦表面有助于从第二光致抗蚀剂材料产生准确，精确和“高保真”的光致抗蚀剂特征。

公开(公告)号：US20080259458A1

公开(公告)日：2008-10-23

申请号：US11788355

申请日：2007-04-18

申请人： Bruno M. LaFontaine ,  Ryoung-Han Kim ,  Jongwook Kye

发明人： Bruno M. LaFontaine ,  Ryoung-Han Kim ,  Jongwook Kye

IPC分类号： G02B5/18

CPC分类号： G03F7/70158 ,  G03F7/70091

摘要： According to one exemplary embodiment, an EUV (extreme ultraviolet) optical element in a light path between an EUV light source and a semiconductor wafer includes a reflective film having a number of bilayers. The reflective film includes a pattern, where the pattern causes a change in incident EUV light from the EUV light source, thereby controlling illumination at a pupil plane of an EUV projection optic to form a printed field on the semiconductor wafer. The EUV optical element can be utilized in an EUV lithographic process to fabricate a semiconductor die.

摘要翻译： 根据一个示例性实施例，EUV光源和半导体晶片之间的光路中的EUV（极紫外）光学元件包括具有多个双层的反射膜。 反射膜包括图案，其中图案引起来自EUV光源的入射EUV光的变化，由此控制EUV投影光学器件的光瞳面处的照明，以在半导体晶片上形成印刷场。 EUV光学元件可以用于EUV光刻工艺以制造半导体管芯。

公开(公告)号：US07422829B1

公开(公告)日：2008-09-09

申请号：US10859276

申请日：2004-06-02

申请人： Carl P. Babcock ,  Jongwook Kye

发明人： Carl P. Babcock ,  Jongwook Kye

IPC分类号： G03F1/00 ,  G06F17/20

CPC分类号： G03F7/70625 ,  G03F1/36 ,  G03F1/70

摘要： A method of adjusting a reticle layout to correct for flare can include determining a localized reticle pattern density across the reticle layout and determining a relationship between reticle pattern density and edge adjustment for the photolithography apparatus being used. For a given feature of the reticle layout, an edge of the feature can be adjusted by a given amount based on the localized reticle pattern density adjacent the given feature. This method allows for a rule-based optical proximity correction (OPC) approach to compensate for long-range and short-range flare within a photolithography apparatus.

摘要翻译： 调整掩模版布局以校正火炬的方法可以包括确定横跨标线布局的局部掩模图案密度，并确定所使用的光刻设备的掩模版图案密度和边缘调整之间的关系。 对于标线布局的给定特征，可以基于与给定特征相邻的局部掩模版图案密度，将特征的边缘调整给定量。 该方法允许基于规则的光学邻近校正（OPC）方法来补偿光刻设备内的远距离和短距离闪光。

公开(公告)号：US20080171447A1

公开(公告)日：2008-07-17

申请号：US11623036

申请日：2007-01-12

申请人： Thomas Ingolf Wallow ,  Ryoung-han Kim ,  Jongwook Kye ,  Harry Jay Levinson

发明人： Thomas Ingolf Wallow ,  Ryoung-han Kim ,  Jongwook Kye ,  Harry Jay Levinson

IPC分类号： H01L21/31

CPC分类号： H01L21/0273 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/31144

摘要： A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.

摘要翻译： 提供一种形成半导体器件的方法，包括处理具有目标材料的晶片，在目标材料上形成具有保护层的多层光致抗蚀剂结构，以及在多层光致抗蚀剂结构中在目标材料中形成多层凹槽。