HIGH FIDELITY MULTIPLE RESIST PATTERNING
    1.
    发明申请
    HIGH FIDELITY MULTIPLE RESIST PATTERNING 审中-公开
    高清多重电阻图案

    公开(公告)号:US20080292991A1

    公开(公告)日:2008-11-27

    申请号:US11753443

    申请日:2007-05-24

    IPC分类号: G03C5/00 H01L21/31

    摘要: An integrated circuit fabrication process as described herein employs a double photoresist exposure technique. After creation of a first pattern of photoresist features on a wafer, a second photoresist layer is formed over the first pattern of photoresist features. The second photoresist layer is subjected to a reflow step that softens and relaxes the second photoresist material. This reflow step causes the exposed surface of the second photoresist layer to become substantially planar. Thereafter, the second photoresist layer can be exposed and developed to create a second pattern of photoresist features on the wafer. The planar surface of the second photoresist layer, which results from the reflow step, facilitates the creation of accurate, precise, and “high fidelity” photoresist features from the second photoresist material.

    摘要翻译: 本文所述的集成电路制造工艺采用双光致抗蚀剂曝光技术。 在晶片上形成光致抗蚀剂特征的第一图案之后,在光致抗蚀剂特征的第一图案之上形成第二光致抗蚀剂层。 对第二光致抗蚀剂层进行软化和松弛第二光致抗蚀剂材料的回流步骤。 该回流步骤使得第二光致抗蚀剂层的暴露表面变得基本上平坦。 此后,可以对第二光致抗蚀剂层进行曝光和显影以在晶片上产生光致抗蚀剂特征的第二图案。 由回流步骤产生的第二光致抗蚀剂层的平坦表面有助于从第二光致抗蚀剂材料产生准确,精确和“高保真”的光致抗蚀剂特征。

    EUV diffractive optical element for semiconductor wafer lithography and method for making same
    2.
    发明申请
    EUV diffractive optical element for semiconductor wafer lithography and method for making same 审中-公开
    用于半导体晶片光刻的EUV衍射光学元件及其制造方法

    公开(公告)号:US20080259458A1

    公开(公告)日:2008-10-23

    申请号:US11788355

    申请日:2007-04-18

    IPC分类号: G02B5/18

    CPC分类号: G03F7/70158 G03F7/70091

    摘要: According to one exemplary embodiment, an EUV (extreme ultraviolet) optical element in a light path between an EUV light source and a semiconductor wafer includes a reflective film having a number of bilayers. The reflective film includes a pattern, where the pattern causes a change in incident EUV light from the EUV light source, thereby controlling illumination at a pupil plane of an EUV projection optic to form a printed field on the semiconductor wafer. The EUV optical element can be utilized in an EUV lithographic process to fabricate a semiconductor die.

    摘要翻译: 根据一个示例性实施例,EUV光源和半导体晶片之间的光路中的EUV(极紫外)光学元件包括具有多个双层的反射膜。 反射膜包括图案,其中图案引起来自EUV光源的入射EUV光的变化,由此控制EUV投影光学器件的光瞳面处的照明,以在半导体晶片上形成印刷场。 EUV光学元件可以用于EUV光刻工艺以制造半导体管芯。

    Optical polarizer with nanotube array
    3.
    发明授权
    Optical polarizer with nanotube array 有权
    具有纳米管阵列的光学偏振器

    公开(公告)号:US08792161B2

    公开(公告)日:2014-07-29

    申请号:US11709718

    申请日:2007-02-21

    IPC分类号: G02B5/30

    摘要: An optical polarizer positioned before a light source for use in semiconductor wafer lithography including an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.

    摘要翻译: 位于用于半导体晶片光刻的光源之前的光学偏振器,包括排列的纳米管阵列。 排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光,以转换为偏光,用于半导体晶片光刻。 极化量可以通过耦合到排列的纳米管阵列的电压源来控制。 光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。

    Method for forming a high resolution resist pattern on a semiconductor wafer
    4.
    发明授权
    Method for forming a high resolution resist pattern on a semiconductor wafer 有权
    在半导体晶片上形成高分辨率抗蚀剂图案的方法

    公开(公告)号:US08586269B2

    公开(公告)日:2013-11-19

    申请号:US11726433

    申请日:2007-03-22

    IPC分类号: G11B11/105

    CPC分类号: G03F7/38

    摘要: In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.

    摘要翻译: 在一个公开的实施例中,在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中,图案化的辐射由极紫外(EUV)光源提供。 在其它实施例中,图案化辐射源可以是例如电子束或离子束。 在一个实施方案中,聚合物基质是有机聚合物基质,例如苯乙烯,丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中,催化物质可以是例如酸,碱或氧化剂。

    EUV pellicle and method for fabricating semiconductor dies using same
    5.
    发明申请
    EUV pellicle and method for fabricating semiconductor dies using same 有权
    EUV防护薄膜和使用其制造半导体管芯的方法

    公开(公告)号:US20080152873A1

    公开(公告)日:2008-06-26

    申请号:US11646053

    申请日:2006-12-26

    IPC分类号: G03F1/00 B32B3/00 H01L21/50

    摘要: According to one exemplary embodiment, an extreme ultraviolet (EUV) pellicle for use with a lithographic mask comprises a carbon nanotube film. The carbon nanotube EUV pellicle can be mounted on the lithographic mask. The carbon nanotube EUV pellicle protects the lithographic mask from contamination by undesirable particles and also prevents the undesirable particles from forming a focused image on the surface of a semiconductor wafer during fabrication; while advantageously, the carbon nanotube pellicle has a high level of EUV light transmittance.

    摘要翻译: 根据一个示例性实施例,用于光刻掩模的极紫外(EUV)防护薄膜包括碳纳米管膜。 碳纳米管EUV防护薄膜可安装在光刻掩模上。 碳纳米管EUV防护薄膜保护光刻掩模免受不期望的颗粒的污染,并且还防止不期望的颗粒在制造期间在半导体晶片的表面上形成聚焦图像; 同时有利地,碳纳米管薄膜具有高水平的EUV透光率。

    METHOD FOR FORMING AN INTERCONNECT STRUCTURE
    6.
    发明申请
    METHOD FOR FORMING AN INTERCONNECT STRUCTURE 有权
    形成互连结构的方法

    公开(公告)号:US20120058640A1

    公开(公告)日:2012-03-08

    申请号:US12876510

    申请日:2010-09-07

    IPC分类号: H01L21/768

    摘要: A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

    摘要翻译: 用于形成互连结构的方法包括在基底层上形成心轴,在心轴上形成间隔物,使用间隔物作为蚀刻模板在基底层中形成凹陷,并在凹部中形成导电材料。

    DOUBLE EXPOSURE TECHNOLOGY USING HIGH ETCHING SELECTIVITY
    7.
    发明申请
    DOUBLE EXPOSURE TECHNOLOGY USING HIGH ETCHING SELECTIVITY 有权
    使用高蚀刻选择性的双重曝光技术

    公开(公告)号:US20100270652A1

    公开(公告)日:2010-10-28

    申请号:US12762457

    申请日:2010-04-19

    IPC分类号: H01L23/00

    摘要: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.

    摘要翻译: 尺寸小于光刻的化学和光学限制的超细图案通过使用双曝光技术叠加两个光致抗蚀剂图案来形成。 实施例包括在待图案化的目标层上形成第一抗蚀剂图案,在第一抗蚀剂图案上方形成保护覆盖层,在叠层在第一抗蚀剂图案上的覆盖层上形成第二抗蚀剂图案,同时覆盖层保护第一抗蚀剂图案 以相对于第一和第二抗蚀剂图案的高选择性选择性地蚀刻覆盖层,留下由第一和第二抗蚀剂图案限定的超细目标图案,并使用叠加的第一和第二抗蚀剂图案作为掩模蚀刻下面的目标层。

    EUV pellicle and method for fabricating semiconductor dies using same
    8.
    发明授权
    EUV pellicle and method for fabricating semiconductor dies using same 有权
    EUV防护薄膜和使用其制造半导体管芯的方法

    公开(公告)号:US07767985B2

    公开(公告)日:2010-08-03

    申请号:US11646053

    申请日:2006-12-26

    IPC分类号: G03F1/00

    摘要: According to one exemplary embodiment, an extreme ultraviolet (EUV) pellicle for use with a lithographic mask comprises a carbon nanotube film. The carbon nanotube EUV pellicle can be mounted on the lithographic mask. The carbon nanotube EUV pellicle protects the lithographic mask from contamination by undesirable particles and also prevents the undesirable particles from forming a focused image on the surface of a semiconductor wafer during fabrication; while advantageously, the carbon nanotube pellicle has a high level of EUV light transmittance.

    摘要翻译: 根据一个示例性实施例,用于光刻掩模的极紫外(EUV)防护薄膜包括碳纳米管膜。 碳纳米管EUV防护薄膜可安装在光刻掩模上。 碳纳米管EUV防护薄膜保护光刻掩模免受不期望的颗粒的污染,并且还防止不期望的颗粒在制造期间在半导体晶片的表面上形成聚焦图像; 同时有利地,碳纳米管薄膜具有高水平的EUV透光率。

    Double exposure technology using high etching selectivity
    9.
    发明申请
    Double exposure technology using high etching selectivity 有权
    双曝光技术采用高蚀刻选择性

    公开(公告)号:US20070287101A1

    公开(公告)日:2007-12-13

    申请号:US11448786

    申请日:2006-06-08

    IPC分类号: G03F7/26

    摘要: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.

    摘要翻译: 尺寸小于光刻的化学和光学限制的超细图案通过使用双曝光技术叠加两个光致抗蚀剂图案来形成。 实施例包括在待图案化的目标层上形成第一抗蚀剂图案,在第一抗蚀剂图案上方形成保护覆盖层,在叠层在第一抗蚀剂图案上的覆盖层上形成第二抗蚀剂图案,同时覆盖层保护第一抗蚀剂图案 以相对于第一和第二抗蚀剂图案的高选择性选择性地蚀刻覆盖层,留下由第一和第二抗蚀剂图案限定的超细目标图案,并使用叠加的第一和第二抗蚀剂图案作为掩模蚀刻下面的目标层。

    Multilayer interconnect structure and method for integrated circuits
    10.
    发明授权
    Multilayer interconnect structure and method for integrated circuits 有权
    集成电路的多层互连结构和方法

    公开(公告)号:US08664113B2

    公开(公告)日:2014-03-04

    申请号:US13096898

    申请日:2011-04-28

    申请人: Ryoung-Han Kim

    发明人: Ryoung-Han Kim

    IPC分类号: H01L21/4763

    摘要: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.

    摘要翻译: 通过以下方式形成多层互连结构:提供其上具有用于支撑具有下导体MN,上导体MN + 1,电介质中间层(DIL)和通过导体VN + 1 / N互连的多层互连的第一电介质的衬底。 下导体MN具有位于第一电介质的第二上表面下方的凹部中的第一上表面。 DIL形成在第一和第二表面之上。 通过DIL从上导体MN + 1的所需位置蚀刻空腔,露出第一表面。 空腔填充另外的电导体以形成上导体MN + 1,并且连接通孔导体VN + 1 / N与第一上表面电接触。 下导体MN和通孔导体VN + 1 / N之间的关键尺寸被延长。 泄漏电流和电迁移减少。