公开(公告)号：US07603603B2

公开(公告)日：2009-10-13

申请号：US11441815

申请日：2006-05-26

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC classification number: G11C29/12015 ,  G11C29/003 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.

Abstract translation: 可配置的存储器架构包括集成在所述存储器中的内置测试机制，以在随机存取存储器（RAM）中支持非常有效的内置自检，在面积和速度方面大大减少了开销。 存储器由于在解码中产生的毛刺（有时表现为无效时钟并破坏同步系统的功能的有害脉冲），位线的慢预充电或读出放大器的慢感测，可能会高速故障。 内存架构包含结构化DFT技术，以分别检测这些故障。

公开(公告)号：US07602162B2

公开(公告)日：2009-10-13

申请号：US11604655

申请日：2006-11-27

Applicant: Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

Inventor： Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

IPC: G05F1/573

CPC classification number: G05F1/573

Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.

Abstract translation: 具有N型传输晶体管的线性稳压器包括过流保护电路。 电流吸收器用作过电流状态的指示器，并且耦合到线性稳压器的输出。 该指示器耦合到控制通过输出负载的电流的反馈逻辑电路。 过电流保护电路广泛地使用N型器件用于各种部件，包括电路中的输出驱动级。 这导致过流保护电路的面积减小。

公开(公告)号：US07598816B2

公开(公告)日：2009-10-06

申请号：US11638306

申请日：2006-12-12

Applicant: Nitin Agarwal ,  Kallol Chatterjee

Inventor： Nitin Agarwal ,  Kallol Chatterjee

IPC: H03L7/08

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.

Abstract translation: 锁相环（PLL）电路包括用于防止电荷泵操作中的错误状况的电路。 通过添加用于相位频率检测器和电荷泵之间的连接的延迟元件来修改PLL电路。 还包括数字逻辑电路以提供用于环路滤波器的时钟信号，其中时钟信号具有对应于来自相位 - 频率检测器的任一个输出信号的较早出现的上升沿的上升沿。

公开(公告)号：US07545180B2

公开(公告)日：2009-06-09

申请号：US11861924

申请日：2007-09-26

Applicant: Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

IPC: G01R19/00

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/413

Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage. The amplifier further includes a pull down circuit and a delay circuit. The delay circuit produces delay between two control signals. The circuit includes a first NOT gate and a second NOT gate operatively coupled to a first latch output node and a second latch output node respectively to provide an output data corresponding to a data stored in a memory cell.

Abstract translation: 读出放大器电路提供具有低电容和低分辨率时间的高速读取操作的高速感测。 读出放大器电路包括具有彼此交叉耦合的第一反相器电路和第二反相器电路的锁存电路。 放大器电路包括分别可操作地耦合到第一反相器电路和第二反相器电路的第一放电装置和第二放电装置。 放大器电路还包括可操作地耦合在第一放电器件和位线之间的第一PMOS晶体管和可操作地耦合在第二放电器件和互补位线之间的第二PMOS晶体管。 放大器电路还包括可操作地耦合在第一放电装置和接地电压之间的第一NMOS晶体管，可操作地耦合在第二放电装置和接地电压之间的第二NMOS晶体管。 放大器还包括下拉电路和延迟电路。 延迟电路在两个控制信号之间产生延迟。 电路包括分别操作地耦合到第一锁存器输出节点和第二锁存器输出节点的第一NOT门和第二NOT门，以提供对应于存储在存储器单元中的数据的输出数据。

公开(公告)号：US07519896B2

公开(公告)日：2009-04-14

申请号：US11233314

申请日：2005-09-22

Applicant: Shashi Kiran Rao Soogoori

Inventor： Shashi Kiran Rao Soogoori

IPC: H03M13/03

CPC classification number: H03M13/2903 ,  H03M13/2957

Abstract: A turbo encoder includes multiple interleaved parallel concatenated recursive systematic convolutional encoders wherein each recursive systematic convolutional encoder is provided with an LUT that simultaneously provides the output bit pattern as well as the next state value corresponding to a defined set of multiple input bits and present state for operating the recursive systematic convolutional encoder. Thus, the approach works with LUTs, which do the job of both puncturing and multiplexing for four input bits at a time. The proposed approach may operate almost four times faster than the conventional approach, which can handle only one input bit at a time.

Abstract translation: turbo编码器包括多个交错并行连接的递归系统卷积编码器，其中每个递归系统卷积编码器都具有一个LUT，该LUT同时提供输出位模式以及下一个对应于一组定义的多个输入位的状态值， 运行递归系统卷积编码器。 因此，该方法与LUT一起工作，LUT一次执行四个输入位的打孔和多路复用。 所提出的方法可以比常规方法快几乎四倍，其一次只能处理一个输入位。

公开(公告)号：US20090076753A1

公开(公告)日：2009-03-19

申请号：US12135418

申请日：2008-06-09

Applicant: Narayanan Vijayaraghavan ,  Balwant Singh

Inventor： Narayanan Vijayaraghavan ,  Balwant Singh

IPC: G01R31/317

CPC classification number: G01R31/31715

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

Abstract translation: 本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。 测试电路包括寄存器组，中央处理控制器（CPC），字符转换模块，延迟表征模块和字符频率模块。 注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。 根据输入指令，CPC对IUT应用激励，IUT的输出由本地表征模块（CHARMODULE）用于提取所需的特性参数，例如测量电压上升/下降时间的字符转换模块， 单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成，从而大大降低了测试设置和输出处理时间。 测试电路可以在多种模式下工作，以选择这些模块之一。

公开(公告)号：US20080290915A1

公开(公告)日：2008-11-27

申请号：US12016004

申请日：2008-01-17

Applicant: Kallol Chatterjee ,  Tanmoy Sen

Inventor： Kallol Chatterjee ,  Tanmoy Sen

IPC: H03L7/095

CPC classification number: H03L7/093 ,  H03L7/10

Abstract: A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles.

Abstract translation: 一种用于减少锁相环（PLL）系统的重新锁定时间的系统和方法，该系统包括具有捕获控制电压模块，力控制电压模块，环路滤波器模块和定时器的电路。 捕捉控制电压模块在PLL的锁定时间期间将控制电压（VCO的电压输入）与预定义的电压电平进行比较，并同时存储最接近控制电压的电压电平。 PLL锁定后，存储的电压变得稳定。 在断电被释放后，力控制电压模块会在非常短的时间内强制存储控制电压在环路滤波器上，从而减少PLL的重新锁定时间。 环路滤波器模块稳定控制电压。 然后，定时器在预定义的时钟周期数之后发送超时信号来关闭力控制电压模块。

公开(公告)号：US20080282023A1

公开(公告)日：2008-11-13

申请号：US11801687

申请日：2007-05-09

Applicant: Sudeep Biswas ,  Angelo Di Sena ,  Domenico Manna

Inventor： Sudeep Biswas ,  Angelo Di Sena ,  Domenico Manna

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06F2212/7211

Abstract: A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.

Abstract translation: 提出了一种基于闪速存储器来恢复存储设备的操作的解决方案。 存储装置模拟映射到闪速存储器的物理存储器空间的逻辑存储器空间（包括具有多个逻辑扇区的多个逻辑块），每个逻辑块包括多个物理块，每个具有多个 用于存储逻辑扇区的不同版本的物理扇区）。 相应的方法通过检测用于损坏的逻辑块（由存储设备的故障导致）的多个冲突的物理块开始。 该方法通过确定多个有效性索引（指示存储在冲突的物理块中的损坏的逻辑块的逻辑扇区的最后版本的数量）来继续。 根据有效性指标选择一个以上的冲突物理块。 所选冲突的物理块然后与损坏的逻辑块相关联。 最后，每个未选择的冲突物理块被丢弃。

公开(公告)号：US07403433B2

公开(公告)日：2008-07-22

申请号：US11617234

申请日：2006-12-28

Applicant: Nasim Ahmad

Inventor： Nasim Ahmad

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C7/227 ,  G11C8/10

Abstract: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation. Recovery operation for the next cycle is then started.

Abstract translation: 提供了一种用于半导体存储器的自定时写入架构及其提供方法。 半导体存储器的核心区域包括正常存储单元阵列和虚拟列。 虚拟列由两个块块A和块B组成。块A由写入操作期间写入数据的N个虚拟单元的簇组成。 虚拟列中的剩余单元一起形成块B，其用于为虚拟位线提供负载。 在写入操作期间，生成伪字线以使得块A的虚拟存储器单元。然后使伪位线行进一般存储器阵列中的行数的一半，然后使其返回。 然后在块A中的所有虚拟单元中写入伪数据。同时，还访问正常存储单元，并将实际数据写入其中。 一旦写入操作完成，就产生一个W复位信号，以指示写操作成功完成。 然后开始下一个循环的恢复操作。

公开(公告)号：US07394291B2

公开(公告)日：2008-07-01

申请号：US11615680

申请日：2006-12-22

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/0175

CPC classification number: H03K19/00315

Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

Abstract translation: 高耐压输出缓冲器使用衬底电压控制电路来控制输出缓冲器中的晶体管的衬底上的电压。 输出缓冲器的电路使得任何晶体管的任何两个端子之间的电压不允许超过输出缓冲器的电源电压。 同时，输出缓冲器的晶体管的源极或漏极的电压不允许超过其衬底电压。 所提出的用于输出缓冲器的电路可以容忍高于其工作电压的电压。 新颖的电路使用更少的硬件并防止电路中的功耗。