公开(公告)号：US20060091969A1

公开(公告)日：2006-05-04

申请号：US10978972

申请日：2004-11-01

Applicant: John Kenney ,  Viswabharath Reddy ,  Ward Titus

Inventor： John Kenney ,  Viswabharath Reddy ,  Ward Titus

IPC: H03B5/08

CPC classification number: H03B5/1228 ,  H03B5/1209 ,  H03B5/1215 ,  H03B5/1225 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266

Abstract: A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.

公开(公告)号：US06992532B2

公开(公告)日：2006-01-31

申请号：US10631833

申请日：2003-08-01

Applicant: Kaare Tais Christensen

Inventor： Kaare Tais Christensen

IPC: H03B5/08

CPC classification number: H03J5/244 ,  H01L23/4824 ,  H01L2924/0002 ,  H03B5/1212 ,  H03B5/1231 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/366 ,  H03B2201/0266 ,  H03J2200/10 ,  H01L2924/00

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

公开(公告)号：US20050093639A1

公开(公告)日：2005-05-05

申请号：US10952447

申请日：2004-09-29

Applicant: Gojin Arakawa

Inventor： Gojin Arakawa

IPC: H03K3/00 ,  H03B1/00 ,  H03B5/02 ,  H03B5/12 ,  H03B5/18 ,  H03K17/62

CPC classification number: H03B25/00 ,  H03B2200/0048 ,  H03B2201/0266

Abstract: A voltage controlled oscillator and a switching circuit therein are capable of surely disabling the unselected circuit. In the case where a switching voltage is low, a first PNP transistor is turned on, and a voltage is applied to a first circuit connecting to the collector of the first PNP transistor. A second PNP transistor is then turned off, and no voltage is applied to a second circuit connecting the collector of the second PNP transistor. In contrast, in the case where the switching voltage is high, the first PNP transistor is turned off, and voltage is not applied to the first circuit. The second PNP transistor is turned on, and a voltage is applied to the second circuit.

Abstract translation: 其中的压控振荡器和开关电路能够确定地禁用未选择的电路。 在开关电压低的情况下，第一PNP晶体管导通，并且向连接到第一PNP晶体管的集电极的第一电路施加电压。 然后关闭第二PNP晶体管，并且没有电压施加到连接第二PNP晶体管的集电极的第二电路。 相反，在开关电压高的情况下，第一PNP晶体管截止，并且不向第一电路施加电压。 第二PNP晶体管导通，并且向第二电路施加电压。

公开(公告)号：US20050083105A1

公开(公告)日：2005-04-21

申请号：US10964704

申请日：2004-10-15

Applicant: Junichi Matsuura ,  Eiichi Kaminishi ,  Noriyuki Fujita

Inventor： Junichi Matsuura ,  Eiichi Kaminishi ,  Noriyuki Fujita

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/93 ,  H01L29/94 ,  H03B1/00 ,  H03B5/32 ,  H03B5/30

CPC classification number: H03B5/32 ,  H03B2201/0266 ,  H03J2200/10

Abstract: To provide a voltage controlled variable capacitor which can change a capacitance value thereof in a wide controlled voltage range and control the capacitance value easily with a high precision without complicating the circuit configuration thereof, and to provide a voltage controlled variable capacitor which can change a capacitance value thereof with a good linearity. The voltage controlled varactor is configured in a manner that varactors VCk, each formed by a series connection of a fixed capacitor Ck (k=1, 2, - - - , n) and a MOS transistor Mk of N channel type, are connected in parallel. The MOS transistors M1 to Mn are configured in a manner that gate widths W are same but gate lengths L1 to Ln are elongated sequentially (that is, L1

Abstract translation: 为了提供可以在宽的受控电压范围内改变其电容值并且以高精度容易地控制电容值而不使其电路结构复杂化的电压控制可变电容器，并且提供可以改变电容的电压控制的可变电容器 其值具有良好的线性。 压控变容二极管被配置为使得由固定电容器Ck（k = 1,2，...，n）和N沟道型的MOS晶体管Mk的串联连接形成的变容二极管VCk连接在 平行。 MOS晶体管M 1〜Mn以栅极宽度W相同但栅极长度L 1〜Ln顺序延长（即，L 1

公开(公告)号：US20040212417A1

公开(公告)日：2004-10-28

申请号：US10809838

申请日：2004-03-26

Inventor： Arya R. Behzad

IPC: H04B003/00

CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

公开(公告)号：US06759904B2

公开(公告)日：2004-07-06

申请号：US10183552

申请日：2002-06-28

Applicant: Arya R. Behzad

Inventor： Arya R. Behzad

IPC: H03F345

CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.频率规划提供额外的图像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合差分对放大器实现的失真消除，其具有与差分对源的电流转向结合动态修改的Vds。

公开(公告)号：US06624484B2

公开(公告)日：2003-09-23

申请号：US09917703

申请日：2001-07-31

Applicant: Kaare Tais Christensen

Inventor： Kaare Tais Christensen

IPC: H01L2976

CPC classification number: H03J5/244 ,  H01L23/4824 ,  H01L2924/0002 ,  H03B5/1212 ,  H03B5/1231 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/366 ,  H03B2201/0266 ,  H03J2200/10 ,  H01L2924/00

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Abstract translation: 一种包括第一电抗，第二电抗和绝缘栅场效应晶体管的调谐电路，其具有布置成接收控制信号的栅极。 第一电抗连接在场效应晶体管的源极和第一节点之间。 第二电抗具有与第一电抗相同的值，并连接在场效应晶体管的漏极和第二节点之间。 第一和第二节点布置成经历平衡的交流信号。 导通场效应晶体管具有使第一和第二电抗在电路中有效的效果，反之亦然。

公开(公告)号：US06525609B1

公开(公告)日：2003-02-25

申请号：US09547968

申请日：2000-04-12

Applicant: Arya R. Behzad

Inventor： Arya R. Behzad

IPC: H03F345

CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.频率规划提供额外的图像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合差分对放大器实现的失真消除，其具有与差分对源的电流转向结合动态修改的Vds。

公开(公告)号：US20030025567A1

公开(公告)日：2003-02-06

申请号：US10201467

申请日：2002-07-23

Inventor： Kuichi Kubo ,  Fumio Asamura

IPC: H03B005/32

CPC classification number: H03B5/368 ,  H03B2201/0266

Abstract: A crystal oscillator has a quartz-crystal unit, a first oscillating capacitor connected between a first end of the crystal unit and a reference potential point, a second oscillating capacitor connected between a second end of the crystal unit and the reference potential point, a CMOS inverter connected parallel to the crystal unit, and a feedback resistor connected across the inverter. The crystal oscillator can easily be incorporated into integrated circuits and has an increased variable oscillation frequency range. The crystal oscillator also has an adjustable capacitive assembly having selectable capacitances which is connected parallel to a combined capacitor comprising the first and the second oscillating capacitors.

Abstract translation: 晶体振荡器具有石英晶体单元，连接在晶体单元的第一端和参考电位点之间的第一振荡电容器，连接在晶体单元的第二端和参考电位点之间的第二振荡电容器，CMOS 逆变器并联到晶体单元，反馈电阻连接在逆变器上。 晶体振荡器可以方便地集成到集成电路中，并且具有增加的可变振荡频率范围。 晶体振荡器还具有可调电容组件，其具有与包括第一和第二振荡电容器的组合电容器并联连接的可选电容。

公开(公告)号：US06441671B1

公开(公告)日：2002-08-27

申请号：US09542531

申请日：2000-04-04

Applicant: Ali Rastegar

Inventor： Ali Rastegar

IPC: H03F130

CPC classification number: H03B5/08 ,  H03B5/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03B2201/0266 ,  H03F3/191 ,  H03J1/0008 ,  H03J2200/10 ,  H03M1/804

Abstract: A programming method (250) for digitally programming the adjustment of an electronic trim capacitor (212, 314, 414). In an initial step (252), programming is initiated by setting an enable terminal (224). In subsequent steps (254, 256) a pulse signal (226) then applied to a program terminal (222) and the number of pulses (228) provided to the programming terminal (222) while the enable terminal (224) is set determines the total number of capacitance increments for which the electronic trim capacitor (212, 314, 414) is programmed. The electronic trim capacitor (212, 314, 414) may be incorporated into an integrated circuit (12, 312) or a module (412) and the electronic trim capacitor (212, 314, 414) may be programmed and used “in situ” in a more general circuit (1) such as an oscillator (301) or an amplifier (401).

Abstract translation: 一种用于数字编程电子微调电容器（212,314,414）的调整的编程方法（250）。 在初始步骤（252）中，通过设置使能终端（224）来启动编程。 在随后的步骤（254,256）中，随后施加到程序终端（222）的脉冲信号（226），并且在使能终端（224）被置位时提供给编程终端（222）的脉冲数（228）决定了 电子微调电容器（212,314,414）被编程的电容增量的总数。 电子微调电容器（212,314,414）可以被并入到集成电路（12,312）或模块（412）中，并且电子微调电容器（212,314,414）可以被“编程和原位”使用， 在诸如振荡器（301）或放大器（401）的更通用的电路（1）中。