公开(公告)号：US07171183B2

公开(公告)日：2007-01-30

申请号：US10407097

申请日：2003-04-03

申请人： Hung-Ming (Ed) Chien

发明人： Hung-Ming (Ed) Chien

IPC分类号： H04B7/00

CPC分类号： H03L7/146 ,  H03L7/0891 ,  H03L7/1976

摘要： A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value. The loop filter is operably coupled to produce a control voltage based on at least some of: the positive current, the negative current, and the non-zero offset current. The voltage controlled oscillator produces an output oscillation based on the control voltage. The fractional-N divider module operably coupled to divided the output oscillation by a fractional N value to produce the feedback oscillation.

摘要翻译： 线性分数N合成器包括相位和频率检测模块，电荷泵电路，环路滤波器，压控振荡器和分数N分频器。 相位和频率检测模块可操作地耦合，以基于参考振荡和反馈振荡之间的相位差和/或频率差产生充电信号，充电停止信号或关闭信号。 当接收到充电信号时，电荷泵电路被可操作地耦合以产生正电流，当接收到充电停止信号时产生负电流，以及当接收到关闭信号时产生非零偏移电流。 电荷泵包括电阻器和控制模块。 电阻器提供非零偏移电流，并且控制模块将非零偏移电流保持在基本恒定的值。 环路滤波器可操作地耦合以产生基于以下中的至少一些的控制电压：正电流，负电流和非零偏移电流。 压控振荡器基于控制电压产生输出振荡。 分数N分频器模块可操作地耦合以将输出振荡除以分数N值以产生反馈振荡。

公开(公告)号：US07126429B2

公开(公告)日：2006-10-24

申请号：US10951798

申请日：2004-09-29

申请人： Krste Mitric

发明人： Krste Mitric

IPC分类号： H03B7/07

CPC分类号： H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/143 ,  H03L7/146 ,  H04J3/0688

摘要： A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.

摘要翻译： 具有快速锁定功能的数字锁相环包括用于产生锁相到输入参考时钟的输出信号的数字控制振荡器，用于测量所述输入参考时钟和反馈时钟之间的相位差的相位检测器和用于 产生用于数字控制振荡器的控制信号环路滤波器包括用于开发与所述相位差成比例的第一信号的比例电路，用于从所述第一信号产生第二积分信号的积分器，用于将所述第一和第二信号加到 开发所述控制信号，以及加权电路，优选地是线性乘法器，用于在积分器的输入处选择性地向第一信号增加额外的权重，以缩短锁相环在快速锁定模式下的锁定时间并快速实现 稳定频率在保持模式。

公开(公告)号：US06643347B2

公开(公告)日：2003-11-04

申请号：US10025583

申请日：2001-12-26

申请人： Takeo Ohishi

发明人： Takeo Ohishi

IPC分类号： H04L700

CPC分类号： H04N21/6336 ,  H03L7/095 ,  H03L7/146 ,  H03L7/181 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/6112

摘要： A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. A first oscillator generates a reference clock signal having a frequency depending on a control signal. A second oscillator generates a basic signal having a fixed frequency. A first circuit loop operates for generating a first error signal in response to the reference clock signal and the extracted reference information, and for feeding the first error signal in response to the reference clock signal and the control signal. A second device operates for enabling one of the first circuit loop and the second circuit loop and disabling the other.

摘要翻译： 时钟信号发生装置包括用于从输入数字信号中提取参考信息的第一装置。 第一振荡器产生具有取决于控制信号的频率的参考时钟信号。 第二振荡器产生具有固定频率的基本信号。 第一电路环路用于响应于参考时钟信号和所提取的参考信息产生第一误差信号，并且响应于参考时钟信号和控制信号馈送第一误差信号。 第二设备用于启用第一电路回路和第二回路回路中的一个并禁用另一个回路。

公开(公告)号：US06597754B1

公开(公告)日：2003-07-22

申请号：US09217233

申请日：1998-12-21

申请人： Stephen T. Janesch ,  Paul Schnizlein

发明人： Stephen T. Janesch ,  Paul Schnizlein

IPC分类号： H03D324

CPC分类号： H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

摘要： A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data. The method includes steps of (a) performing a carrier recovery during the preamble of a received frame, (b) storing a digital word indicative of a recovered carrier frequency at the end of the preamble, (c) continuing the carrier recovery during the payload portion of the received frame, (d) using the stored digital word to set an initial frequency for carrier recovery at the start of a subsequent frame, and (e) repeating said steps (a)-(d) for each frame in the series of data frames.

摘要翻译： 用于补偿TDD和TDMA无线电收发器中的频率牵引的载波恢复回路。 数字载波恢复回路包括信号输入，数字控制振荡器（DCO），相位检测器，环路滤波器和存储器。 存储器存储DCO的初始化值，使得其频率可以在接收帧的开始处被快速初始化。 该初始化值优选地是用于DCO的控制信号的采样或由相位检测器生成的相位误差信号的积分值的采样。 还描述了一种用于补偿TDD或TDMA无线电收发器中的频率牵引的方法。 收发器优选地接收具有前同步码的数据帧，后面是保存发送数据的有效载荷部分。 该方法包括以下步骤：（a）在接收到的帧的前导码中执行载波恢复，（b）在前导码的末尾存储指示恢复的载波频率的数字字，（c）在有效载荷期间继续载波恢复 （d）使用所存储的数字字来在后续帧的开始处设置用于载波恢复的初始频率，以及（e）对于该系列中的每个帧重复所述步骤（a） - （d） 的数据帧。

公开(公告)号：US06414554B1

公开(公告)日：2002-07-02

申请号：US09820232

申请日：2000-03-23

申请人： Keith A. Tilley ,  Rajesh H. Zele ,  Walter H. Kehler, Jr.

发明人： Keith A. Tilley ,  Rajesh H. Zele ,  Walter H. Kehler, Jr.

IPC分类号： H03L700

CPC分类号： H03J7/04 ,  H03J2200/29 ,  H03L7/146

摘要： A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

摘要翻译： 接收机包括具有主VCO（210）和具有次级VCO（216）的次级环路（224）的主回路（222）。 接收机瞬间锁定进入的RF信号（228），然后采样并存储施加到主VCO（210）的校正电压（240）。 然后，主回路（222）进入非相位锁定操作模式，并且存储的校正电压通过接收自动调谐电路（218）施加到主VCO（210），以进入RF信号的持续时间 228）。 这有效地校准接收机的LO频率（230）到输入RF信号频率（228）。

公开(公告)号：US06396890B1

公开(公告)日：2002-05-28

申请号：US09352173

申请日：1999-07-12

申请人： Neil William Ashley Turner

发明人： Neil William Ashley Turner

IPC分类号： H03D324

CPC分类号： H03L7/146

摘要： A frequency synthesizer of the phase locked loop type and particularly useful for frequency hopping applications includes means (8) for achieving fast frequency and phase lock. In one embodiment the synthesizer is steered to a new frequency value by a DAC 10 which controls a VCO (5) input voltage. Subsequently, the phase of the synthesizer output is locked to that of the reference frequency oscillator (1) by resetting the feedback frequency divider (6) at the point in time when a rising edge of the reference frequency is detected. In a second embodiment, rapid frequency and phase lock is achieved by resetting the feedback frequency divider (6) on every rising edge of the reference frequency while the feedback loop is disabled, until the detected phase difference between the reference frequency and the divided VCO frequency reaches a minimum value.

摘要翻译： 锁相环类型的频率合成器特别适用于跳频应用，包括实现快速频相锁相的装置（8）。 在一个实施例中，通过控制VCO（5）输入电压的DAC 10将合成器转向新的频率值。 随后，通过在检测到参考频率的上升沿的时间点复位反馈分频器（6），合成器输出的相位被锁定到参考频率振荡器（1）的相位。 在第二实施例中，通过在反馈环路被禁用的同时在参考频率的每个上升沿复位反馈分频器（6）来实现快速频率和相位锁定，直到检测到的参考频率与分频VCO频率之间的相位差 达到最小值。

公开(公告)号：US20020048338A1

公开(公告)日：2002-04-25

申请号：US10025583

申请日：2001-12-26

申请人： Victor Company of Japan, Ltd

发明人： Takeo Ohishi

IPC分类号： H03D003/24

CPC分类号： H04N21/6336 ,  H03L7/095 ,  H03L7/146 ,  H03L7/181 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/6112

摘要： A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. An oscillator operates for generating a reference clock signal having a frequency depending on a control signal. A second device connected to the first device and the oscillator operates for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first device, and for locking a phase of the reference clock signal to the reference information. A third device connected to the second device operates for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information. A fourth device connected to the second device, a memory, and the third device operates for storing the control signal generated by the second device into the memory when the third device decides that the phase of the reference clock signal is successfully locked to the reference information. A fifth device connected to the memory, the oscillator, and the second device operates for selecting one of the control signal currently generated by the second device and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.

摘要翻译： 时钟信号发生装置包括用于从输入数字信号中提取参考信息的第一装置。 振荡器用于产生具有取决于控制信号的频率的参考时钟信号。 连接到第一设备和振荡器的第二设备响应于由振荡器产生的参考时钟信号和由第一设备提取的参考信息而产生到振荡器的控制信号，并且用于锁定参考时钟的相位 信号给参考信息。 连接到第二设备的第三设备用于确定参考时钟信号的相位是否被成功地锁定到参考信息。 连接到第二设备的第四设备，存储器和第三设备用于当第三设备确定参考时钟信号的相位成功地锁定到参考信息时，将由第二设备产生的控制信号存储到存储器中 。 连接到存储器，振荡器和第二器件的第五器件用于选择当前由第二器件产生的控制信号和存储在存储器中的控制信号之一，并将所选择的控制信号馈送到振荡器。

公开(公告)号：US06356156B2

公开(公告)日：2002-03-12

申请号：US09849173

申请日：2001-05-04

申请人： Jan Wesolowski

发明人： Jan Wesolowski

IPC分类号： H03L708

CPC分类号： H03L7/146 ,  H03L7/107 ,  H03L7/143 ,  H03L7/197 ,  H04J3/0688 ,  H04L7/0331

摘要： Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator, caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

摘要翻译： 公开了用于消除受控频率振荡器的相位瞬变的方法和系统，该方法和系统是当第一参考信号变得损坏或不可用时由第二参考信号替换第一参考信号引起的，并且用于以频率振荡器运行受控频率振荡器， 控制保持模式。 满足在相对宽的频率范围内可调谐的相对低成本的受控频率振荡器并且在保持模式下实现其频率的高稳定性的矛盾要求。

公开(公告)号：US20010015678A1

公开(公告)日：2001-08-23

申请号：US09849173

申请日：2001-05-04

发明人： Jan Wesolowski

IPC分类号： H03L007/08 ,  H03L007/18 ,  H03L007/197

CPC分类号： H03L7/146 ,  H03L7/107 ,  H03L7/143 ,  H03L7/197 ,  H04J3/0688 ,  H04L7/0331

摘要： Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator. caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

摘要翻译： 公开了用于消除受控频率振荡器的相位瞬变的方法和系统。 当第一参考信号被破坏或不可用时，通过用第二参考信号替换第一参考信号，以及用于以频率控制的保持模式运行受控频率振荡器。 满足在相对宽的频率范围内可调谐的相对低成本的受控频率振荡器并且在保持模式下实现其频率的高稳定性的矛盾要求。

公开(公告)号：US6081163A

公开(公告)日：2000-06-27

申请号：US234979

申请日：1999-01-22

申请人： Hitoshi Ujiie ,  Kazuyuki Maruo

发明人： Hitoshi Ujiie ,  Kazuyuki Maruo

IPC分类号： G04G3/02 ,  G04G7/02 ,  H03L1/02 ,  H03L7/085 ,  H03L7/14 ,  H03L7/18 ,  H03L7/07

CPC分类号： G01S19/235 ,  G04G3/022 ,  G04R40/02 ,  G04R40/06 ,  H03L7/085 ,  H03L7/146 ,  H03L7/18 ,  H03L1/022

摘要： A frequency standard generator includes a voltage controlled crystal oscillator (VCXO) for generating high stability output signal, a radio wave receiver to receive a radio wave which includes a high accuracy reference time signal, a time interval measuring circuit which measures a phase difference between the reference time signal and the output signal of the VCXO; a frequency control processor which determines control data based on the phase difference data to phase lock the output signal of the VCXO to the reference time signal, a frequency deviation data generator for compiling the phase difference data to obtain frequency deviation trend data of the VCXO, and a compensation data generator for generating compensation data based on the frequency deviation trend data to compensate frequency changes in said VCXO when the reference time signal is unavailable.

摘要翻译： 频率标准发生器包括用于产生高稳定度输出信号的电压控制晶体振荡器（VCXO），用于接收包括高精度基准时间信号的无线电波的无线电波接收器，测量第二相位差之间的相位差的时间间隔测量电路 参考时间信号和VCXO的输出信号; 频率控制处理器，其基于相位差数据确定控制数据，以将VCXO的输出信号锁定到参考时间信号;频率偏差数据发生器，用于编译相位差数据以获得VCXO的频率偏差趋势数据; 以及补偿数据发生器，用于基于频率偏差趋势数据产生补偿数据，以补偿当基准时间信号不可用时所述VCXO中的频率变化。