公开(公告)号：US10950292B1

公开(公告)日：2021-03-16

申请号：US16710424

申请日：2019-12-11

申请人： Advanced Micro Devices, Inc.

发明人： SeyedMohammad SeyedzadehDelcheh ,  Steven Raasch

IPC分类号： G11C11/40 ,  G11C11/4078 ,  G11C11/406 ,  G06F12/1018 ,  G11C11/408

摘要： An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.

公开(公告)号：US10930337B2

公开(公告)日：2021-02-23

申请号：US16232293

申请日：2018-12-26

申请人： Micron Technology, Inc.

发明人： John F. Schreck ,  George B. Raad

IPC分类号： G11C11/40 ,  G11C11/4091 ,  G11C11/404 ,  G11C11/56 ,  G11C11/408

摘要： Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

公开(公告)号：US10818675B2

公开(公告)日：2020-10-27

申请号：US16530404

申请日：2019-08-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Hung Hsieh ,  Yu-Min Liao ,  Jhon-Jhy Liaw

IPC分类号： G11C11/41 ,  H01L27/11 ,  G11C11/412 ,  G11C11/40

摘要： SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.

公开(公告)号：US10726901B1

公开(公告)日：2020-07-28

申请号：US16528514

申请日：2019-07-31

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt

IPC分类号： G11C11/40 ,  G11C11/402 ,  G11C11/409 ,  G11C5/06

摘要： A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.

公开(公告)号：US10692561B2

公开(公告)日：2020-06-23

申请号：US16032361

申请日：2018-07-11

申请人： Samsung Electronics Co., Ltd.

发明人： Min-soo Jang ,  Eunsung Seo ,  Seungjun Bae

IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C7/10 ,  G11C11/408 ,  H04N5/335

摘要： A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.

公开(公告)号：US10665293B2

公开(公告)日：2020-05-26

申请号：US16565913

申请日：2019-09-10

申请人： Integrated Device Technology, Inc.

发明人： David Chang

IPC分类号： G11C11/40 ,  G11C11/4093 ,  G11C11/4076

摘要： An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

公开(公告)号：US20200159683A1

公开(公告)日：2020-05-21

申请号：US16737182

申请日：2020-01-08

申请人： Micron Technology, Inc.

发明人： Elancheren Durai

IPC分类号： G06F13/40 ,  G11C7/22 ,  G11C11/40 ,  G11C7/10

摘要： An apparatus may include at least one output circuit configured to generate a desired output driver impedance (ODI) during a first operational mode. The least one output circuit may further be configured to independently generate a desired on-die termination (ODT) impedance during a second operational mode. Memory systems, memory devices, electronic systems, and related methods of operation are also described.

公开(公告)号：US10650879B2

公开(公告)日：2020-05-12

申请号：US16328886

申请日：2017-08-30

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Valentin Gherman ,  Marcelino Seif

IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C16/34 ,  G11C7/04 ,  G11C13/00 ,  G06F3/06 ,  G11C16/32 ,  G06F11/30

摘要： A device for controlling the refresh cycles of data stored in a non-volatile memory is provided. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of delivering information representing the measured temperature, and a control module coupled to the temperature sensor capable of using the temperature information with modelling of the impact of the temperature on the retention time of the data in order to determine whether a loss of data is imminent and, if so, in order to generate an alarm.

公开(公告)号：US20200091155A1

公开(公告)日：2020-03-19

申请号：US16690036

申请日：2019-11-20

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： H01L27/108 ,  H01Q1/22 ,  G11C7/00 ,  H01L27/102 ,  G11C11/403 ,  G11C11/40 ,  G11C8/16 ,  G11C11/405 ,  G11C8/10

摘要： Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

公开(公告)号：US10586608B2

公开(公告)日：2020-03-10

申请号：US15802781

申请日：2017-11-03

申请人： Huawei Technologies Co., Ltd.

发明人： Shihai Xiao ,  Yongbing Huang ,  Rui He

IPC分类号： G11C11/40 ,  G11C29/00 ,  G11C11/406 ,  G11C11/4091

摘要： A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.