公开(公告)号：US5434515A

公开(公告)日：1995-07-18

申请号：US201985

申请日：1994-02-25

Applicant: Hiroshi Harada

Inventor： Hiroshi Harada

IPC: H03K17/16 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/01

CPC classification number: H03K19/09448 ,  H03K19/0136

Abstract: For increasing an operation speed of a logic circuit in a case where an output level is shifted from a high level to a low level, a control circuit is made of a combination of a first control transistor and a second control transistor. An input circuit has a local terminal and produces a local signal in response to an input signal to supply the local signal to the local terminal. An output circuit has an output terminal and produces an output signal in response to the input and the local signals to supply the output signal to the output terminal. The first control transistor is connected between the local terminal and the second control transistor and has a first transistor control terminal which is supplied with the output signal for controlling operation of the first control transistor. The second control transistor is connected between the first control transistor and the ground and has a second transistor control terminal which is connected to the input terminal for controlling operation of the second control transistor.

Abstract translation: 为了在输出电平从高电平变为低电平的情况下增加逻辑电路的操作速度，控制电路由第一控制晶体管和第二控制晶体管的组合构成。 输入电路具有本地端子并且响应于输入信号产生本地信号以将本地信号提供给本地端子。 输出电路具有输出端子，并且响应于输入端和本地信号产生输出信号以将输出信号提供给输出端子。 第一控制晶体管连接在本地端子和第二控制晶体管之间，并且具有第一晶体管控制端子，该第一晶体管控制端子被提供有用于控制第一控制晶体管的操作的输出信号。 第二控制晶体管连接在第一控制晶体管和地之间，并具有连接到输入端的第二晶体管控制端，用于控制第二控制晶体管的工作。

公开(公告)号：US5428302A

公开(公告)日：1995-06-27

申请号：US52200

申请日：1993-04-22

Applicant: Yasunobu Nakase

Inventor： Yasunobu Nakase

IPC: H01L21/8249 ,  H01L27/06 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/01

CPC classification number: H03K19/09448

Abstract: A semiconductor logic circuit apparatus includes a plurality of logic circuits each including complementary field effect transistors, and a plurality bipolar transistors associated with the respective ones of the logic circuits. When any one of the outputs of the logic circuits becomes high, an associated bipolar transistor becomes conductive to cause an output terminal of the apparatus to be charged from a voltage supply. With all the outputs of the logic circuits being low, all of the bipolar transistors are non-conductive, and a current supply coupled between the output terminal and ground dicharges charge on the output terminal.

Abstract translation: 半导体逻辑电路装置包括多个逻辑电路，每个逻辑电路各自包括互补的场效应晶体管，以及与各个逻辑电路相关联的多个双极晶体管。 当逻辑电路的任何一个输出变高时，相关联的双极晶体管导通，从而使得装置的输出端子从电压源充电。 在逻辑电路的所有输出为低电平的情况下，所有双极晶体管都是非导通的，并且耦合在输出端子和接地之间的电流供电在输出端子上充电。

公开(公告)号：US5416365A

公开(公告)日：1995-05-16

申请号：US937336

申请日：1992-08-31

Applicant: Michael X. Maida

Inventor： Michael X. Maida

IPC: H03F1/34 ,  H03F3/343 ,  H03F3/50 ,  H03K19/08

CPC classification number: H03F3/50 ,  H03F3/3435

Abstract: When plural emitter follower cascaded transistors are employed as a buffer to drive a capacitive load wherein instabilities can occur. The capacitive loads can result in either ringing or oscillation within such a buffer. The invention relates to applying negative feedback around one or more emitter followers in the cascade. In the preferred embodiment a three stage cascade of emitter followers is employed with negative feedback connected around the penultimate stage.

Abstract translation: 当采用多个发射极跟随器级联晶体管作为缓冲器来驱动其中可能发生不稳定性的电容负载时。 容性负载可能导致在这种缓冲器内振铃或振荡。 本发明涉及在级联中围绕一个或多个发射极跟随器施加负反馈。 在优选实施例中，使用三级串联的发射极跟随器，负反馈连接在倒数第二级周围。

公开(公告)号：US5402018A

公开(公告)日：1995-03-28

申请号：US107143

申请日：1993-08-17

Applicant: Masaru Koyanagi

Inventor： Masaru Koyanagi

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/00 ,  H01L21/82 ,  H03K19/08 ,  H03K19/20 ,  H05B37/02

CPC classification number: G01R31/31701 ,  G06F11/0763 ,  Y10T307/305 ,  Y10T307/359 ,  Y10T307/391 ,  Y10T307/414 ,  Y10T307/461 ,  Y10T307/76

Abstract: A semiconductor integrated circuit is operative in a plurality of different modes. A plurality of select signals whose number corresponds to modes selected from a plurality of different modes are outputted. In response to the select signals, it is detected whether at least two operation modes are selected simultaneously. If so, a detection signal is outputted. In response to this detection signal, the operation of the semiconductor integrated circuit is stopped. Further, in response to the select signal, the semiconductor integrated circuit is activated in a mode by means of a predetermined select signal of these select signals. Further, in response to these select signals, the selected mode can be detected.

Abstract translation: 半导体集成电路以多种不同的模式工作。 输出对应于从多个不同模式中选择的模式的多个选择信号。 响应于选择信号，检测是否同时选择至少两种操作模式。 如果是，则输出检测信号。 响应该检测信号，停止半导体集成电路的动作。 此外，响应于选择信号，半导体集成电路通过这些选择信号的预定选择信号以模式被激活。 此外，响应于这些选择信号，可以检测所选择的模式。

公开(公告)号：US5399918A

公开(公告)日：1995-03-21

申请号：US129664

申请日：1993-09-30

Applicant: Gregory F. Taylor ,  Lawrence T. Clark

Inventor： Gregory F. Taylor ,  Lawrence T. Clark

IPC: G06F15/78 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16

CPC classification number: H03K19/00346 ,  H03K19/09448

Abstract: A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

Abstract translation: 高可靠性，大型风扇，高速BiCMOS电路。 通过向基本逻辑电路的每个输入添加双极晶体管的发射极电容，减少了出现在电路的输出线上的MOS晶体管寄生电容的量。 提供电路以提高反向偏置双极晶体管的基极电压，以减少或消除反向偏置。

公开(公告)号：US5371421A

公开(公告)日：1994-12-06

申请号：US29686

申请日：1993-03-11

Applicant: Harufusa Kondoh ,  Atsushi Ohba

Inventor： Harufusa Kondoh ,  Atsushi Ohba

IPC: H03F3/45 ,  H03K5/02 ,  H03K19/01 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08

CPC classification number: H03K3/021

Abstract: A BiMOS amplifier device includes one stage which can function as both a level-shift and buffer stage and an amplifier stage. The amplifier includes first and second bipolar transistors having their bases connected to first and second input terminals, respectively, having their collectors connected to a point of first potential, and having their emitters connected to the sources of first and second MOS transistors, respectively. The drains of the first and second MOS transistors are connected through respective impedance means to a point of second potential. The gate of each of the MOS transistors is connected to the drain of the other MOS transistor. An output terminal is connected to the drain of at least one of the MOS transistors.

Abstract translation: BiMOS放大器装置包括一个可以起电平移位和缓冲级以及放大级的功能。 放大器包括第一和第二双极晶体管，它们的基极分别连接到第一和第二输入端，它们的集电极分别连接到第一电位点，并且其发射极分别连接到第一和第二MOS晶体管的源极。 第一和第二MOS晶体管的漏极通过相应的阻抗装置连接到第二电势点。 每个MOS晶体管的栅极连接到另一个MOS晶体管的漏极。 输出端连接到至少一个MOS晶体管的漏极。

公开(公告)号：US5338987A

公开(公告)日：1994-08-16

申请号：US150741

申请日：1993-11-12

Applicant: Stephen R. Tomasetti ,  Danny Tsong

Inventor： Stephen R. Tomasetti ,  Danny Tsong

IPC: H03K17/567 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H04B1/40 ,  H03K3/01 ,  H03K19/02

CPC classification number: H03K19/017518

Abstract: A BiCMOS output driver for a transceiver circuit has a pull-up/pull-down circuit with CMOS transistors supplying base current to bipolar pull-up/pull-down transistors. In its quiescent state, the CMOS transistors draw no current. A current mirror circuit comprising a pair of bipolar transistors sized to be a fraction of the pull-up/pull-down transistors is coupled between the input and output of the pull-up/pull-down circuit to prevent exceeding a predetermined current. A speed up circuit comprising CMOS transistors coupled between ground and the base of the bipolar pull-up/pull-down transistors to speed up the shut off of the transistors.

Abstract translation: 用于收发器电路的BiCMOS输出驱动器具有上拉/下拉电路，CMOS晶体管为双极上拉/下拉晶体管提供基极电流。 在静态状态下，CMOS晶体管不产生电流。 包括一对双极晶体管的电流镜电路，其尺寸设置为上拉/下拉晶体管的一部分，被耦合在上拉/下拉电路的输入和输出之间以防止超过预定电流。 一种加速电路，其包括耦合在双极上拉/下拉晶体管的地和基极之间的CMOS晶体管，以加速晶体管的截止。

公开(公告)号：US5311078A

公开(公告)日：1994-05-10

申请号：US878615

申请日：1992-05-05

Applicant: Hiroshi Makino ,  Yasunobu Nakase ,  Kimio Ueda

Inventor： Hiroshi Makino ,  Yasunobu Nakase ,  Kimio Ueda

IPC: H01L21/8249 ,  H01L27/06 ,  H03K19/013 ,  H03K19/0944 ,  H01L29/78 ,  H01L29/02 ,  H03K19/02 ,  H03K19/08

CPC classification number: H03K19/09448 ,  H01L27/0623 ,  H03K19/0136

Abstract: In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.

Abstract translation: 为了获得能够执行高速操作的逻辑电路，P沟道MOSFET（1）和N沟道MOSFET（2）的各个栅极共同地连接到输入节点（6），并且结束 的电阻器（12,13）连接到其各自的漏极。 NPN晶体管（3）和PNP晶体管（4）的各个发射极与电阻器（5）的端部共同连接到输出节点（9），并且电阻器（12,13）的端部连接到 各自的碱基。 P沟道MOSFET（1）的源极和NPN晶体管（3）的集电极共同连接到高电位点（8），而N沟道MOSFET（2）的源极和 PNP晶体管（4）分别连接到低电位点（40）。 电阻器（5,12,13）的各个另一端在节点（7）处共同连接。 因此，当双极晶体管处于导通状态时，输出端子的电位迅速波动。

公开(公告)号：US5287016A

公开(公告)日：1994-02-15

申请号：US861755

申请日：1992-04-01

Applicant: Allan H. Dansky ,  John F. McCabe ,  Kenny K. Shin

Inventor： Allan H. Dansky ,  John F. McCabe ,  Kenny K. Shin

IPC: H03K19/01 ,  H03K3/2885 ,  H03K17/00 ,  H03K17/62 ,  H03K19/08 ,  H03K19/086 ,  H03K19/0944

CPC classification number: H03K19/09448 ,  H03K17/6264 ,  H03K3/2885 ,  H03K2217/0036

Abstract: A process and hold system includes a bipolar logic section which is clocked on and off by a first field effect transistor and a bipolar latch section which is clocked on and off by a second field effect transistor. Emitter coupled logic is used in both the logic and latch sections in order to obtain high speed operation. Each of the field effect transistors is used as an on-off switches which has low impedance between the drain and source thereof when enabled and conducting. Outputs of the logic section are coupled to inputs of the latch section. Complementary clock signals are used to control the first and second field effect transistors so that one of the logic and latch section is enabled at a time. The logic section uses a two level emitter coupled tree configuration in order to increase logic capability. The use of the field effect transistors facilitates the use of a power supply having a voltage level of +3.6 volts. This is contrasted with the typical +5 volt supply used with conventional emitter coupled tree configurations. Accordingly, high speed at reduced power dissipation is achieved using the inventive process and hold system.

Abstract translation: 处理和保持系统包括双极逻辑部分，其由第一场效应晶体管和由第二场效应晶体管定时导通和关断的双极锁存部分引导和断开。 发射极耦合逻辑用于逻辑和锁存部分，以获得高速运行。 每个场效应晶体管用作开关开关，其在启用和导通时在其漏极和源极之间具有低阻抗。 逻辑部分的输出耦合到锁存部分的输入端。 互补时钟信号用于控制第一和第二场效应晶体管，使得逻辑和锁存部分中的一个一次被使能。 逻辑部分使用两级发射器耦合树结构来增加逻辑能力。 使用场效应晶体管有助于使用具有+3.6伏电压电平的电源。 这与常规发射器耦合树结构中使用的典型+5伏电源形成对比。 因此，使用本发明的工艺和保持系统实现了降低的功率消耗的高速度。

公开(公告)号：US5177377A

公开(公告)日：1993-01-05

申请号：US700426

申请日：1991-05-15

Applicant: Hiroyuki Mathuda ,  Shinzou Satou

Inventor： Hiroyuki Mathuda ,  Shinzou Satou

IPC: H03K19/08 ,  H03K19/0944

CPC classification number: H03K19/09448

Abstract: A Bi-CMOS circuit includes a bipolar output stage and a CMOS circuit. The bipolar output stage includes pull-up and pull-down transistors which form an output end. The CMOS circuit receives an input signal and generates a signal for driving the output stage. The CMOS circuit comprises a CMOS inverter for receiving the input signal, a p-channel MOS transistor for driving the pull-up transistor of the bipolar output stage based on the input signal, an n-channel MOS transistor for driving the pull-down transistors of the bipolar output stage based on the input signal, a p-channel MOS transistor for discharging a base of the pull-up transistor based on an output of the CMOS inverter, and an n-channel MOS transistor for discharging a base of the pull-down transistor based on an output of the CMOS inverter.

Abstract translation: 双CMOS电路包括双极性输出级和CMOS电路。 双极性输出级包括形成输出端的上拉和下拉晶体管。 CMOS电路接收输入信号并产生用于驱动输出级的信号。 CMOS电路包括用于接收输入信号的CMOS反相器，用于基于输入信号驱动双极性输出级的上拉晶体管的p沟道MOS晶体管，用于驱动下拉晶体管的n沟道MOS晶体管 基于输入信号的双极性输出级的P沟道MOS晶体管，用于基于CMOS反相器的输出对上拉晶体管的基极进行放电的p沟道MOS晶体管，以及用于放电基极的n沟道MOS晶体管 基于CMOS反相器的输出的下降晶体管。