公开(公告)号：US20050068885A1

公开(公告)日：2005-03-31

申请号：US10676565

申请日：2003-09-30

申请人： Matthew Becker ,  Karl Wyatt

发明人： Matthew Becker ,  Karl Wyatt

IPC分类号： H04J7/00 ,  H04L25/49 ,  H04L25/493 ,  H03C1/52 ,  H04J3/02

CPC分类号： H04L25/4917 ,  H04J7/00 ,  H04L25/493

摘要： According to an embodiment of the invention, a method and apparatus for signal modulation are described. According to an embodiment of the invention, a method comprises producing and transferring a modulated signal. The modulation of the signal is over a plurality of amplitude levels, including at least a first amplitude level, a second amplitude level and a third amplitude level, and over a plurality of time slots, including at least a first time slot, a second time slot, and a third time slot. The modulated signal transitions from the first amplitude level to the second amplitude level in the first phase slot, remains at the second amplitude level in the second time slot, and transitions from the second amplitude level to the third amplitude level in a third time slot.

摘要翻译： 根据本发明的实施例，描述了用于信号调制的方法和装置。 根据本发明的实施例，一种方法包括产生和传送调制信号。 信号的调制在多个幅度水平上，包括至少第一幅度电平，第二幅度电平和第三幅度电平以及多个时隙，包括至少第一时隙，第二时间 插槽和第三个时隙。 调制信号从第一相位时隙中的第一幅度电平转换到第二幅度电平在第二时隙中保持在第二幅度电平，并且在第三时隙中从第二幅度电平转变到第三幅度电平。

公开(公告)号：US5754835A

公开(公告)日：1998-05-19

申请号：US805287

申请日：1997-02-25

申请人： Allan Lin ,  Jay Deng

发明人： Allan Lin ,  Jay Deng

IPC分类号： H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/493 ,  H04L25/52 ,  G06F1/06

CPC分类号： H04L7/0091 ,  H04L25/493 ,  H03L7/0995 ,  H04L7/0008

摘要： A data source circuit and a complementary data recovery circuit which can transmit and receive data at a higher rate than a conventional data source circuit which uses similar fabrication technology. A data source circuit of the present invention has an input for receiving a periodic source clock signal having a period T; a synchronization signal generator for generating, based on said downstream-clock signal, a series of one or more periodic synchronization signals having periods substantially equal to T, each synchronization signal being delayed from a previous synchronization signal; and a transmitter for transmitting one or more sub-words of a multi-bit data word, each sub-word having one or more bits, separate ones of said one or more sub-words being transmitted responsive to separate progressively delayed combined pairs of said synchronization signals. In a preferred embodiment of the present invention particularly suited for use in a point to point (e.g. a ring-type) data network, a recovery circuit and a source circuit are integrated as a receiver/retransmission node.

摘要翻译： 数据源电路和互补数据恢复电路，其能够以比使用类似制造技术的常规数据源电路更高的速率发送和接收数据。 本发明的数据源电路具有用于接收具有周期T的周期性源时钟信号的输入端; 同步信号发生器，用于基于所述下行时钟信号产生一系列具有基本上等于T的周期的周期性同步信号，每个同步信号从先前的同步信号延迟; 以及发送器，用于发送多比特数据字的一个或多个子字，每个子字具有一个或多个比特，所述一个或多个子字中的不同的子字响应于分离的逐渐延迟的所述组合对而被发送 同步信号 在本发明的一个优选实施例中，特别适用于点对点（例如环型）数据网络，恢复电路和源电路被集成为接收机/重传节点。

公开(公告)号：US5729371A

公开(公告)日：1998-03-17

申请号：US500437

申请日：1995-07-10

申请人： Takashi Yoshida ,  Noboru Kanzaki ,  Kenji Asanuma ,  Eiichi Nabeta

发明人： Takashi Yoshida ,  Noboru Kanzaki ,  Kenji Asanuma ,  Eiichi Nabeta

IPC分类号： H04B10/50 ,  H04B10/079 ,  H04B10/2507 ,  H04B10/40 ,  H04B10/516 ,  H04B10/524 ,  H04B10/556 ,  H04B10/564 ,  H04B10/60 ,  H04B10/61 ,  H04B10/69 ,  H04L25/493 ,  H04B10/00

CPC分类号： H04L25/493 ,  H04B10/502 ,  H04B10/504 ,  H04B10/508 ,  H04B10/524 ,  H04B10/564

摘要： An optical communications device is disclosed which is equipped with a transmission unit adapted to send binary-coded electrical pulse signals to another optical communications device in the form of optical pulse signals. The transmission unit includes a modulator for producing an electrical pulse signal of a narrow pulse width only at each of rising and falling edges in the binary-coded electrical pulse signals and an electro-optic converter for converting the electrical pulse signal of a narrow pulse width into an optical pulse signal of a narrow pulse signal. As an alternative, the transmission unit includes a modulator which produces an electrical pulse signal of a narrow pulse width for each bit in the binary-coded electrical pulse signals only when it is at a high level and an electro-optic converter which converts the electrical pulse signal of a narrow pulse width into an optical pulse signal of a narrow pulse width.

公开(公告)号：US4503546A

公开(公告)日：1985-03-05

申请号：US471128

申请日：1983-03-01

申请人： Hiroki Yoshine ,  Yoshitaka Takasaki ,  Yasushi Takahashi ,  Mitsuo Yamada ,  Katsuyuki Nagano

发明人： Hiroki Yoshine ,  Yoshitaka Takasaki ,  Yasushi Takahashi ,  Mitsuo Yamada ,  Katsuyuki Nagano

IPC分类号： H03M5/16 ,  H04B10/07 ,  H04B10/524 ,  H04B10/556 ,  H04B10/564 ,  H04L25/49 ,  H04L25/493 ,  H03K13/02

CPC分类号： H04L25/4906 ,  H04L25/49

摘要： A two-level alternate mark inversion signal transmission system wherein binary pulses of "1" and "0" levels are converted into a pulse signal in which one coded information value has its polarity inverted at a period T and the other has its polarity reversed at a period T/2, and the converted signal is transmitted. In order to facilitate an automatic gain control operation and the proper and reliable extraction of a timing signal on the receiving side of the system even when the zero binary pulses have successively arisen in the signal processed on the transmitting side, the alternate mark inversion signal is converted into a specified code (zero substitution) signal when the zero binary pulses have succeeded one another for a predetermined number of times, while on the receiving side, a received signal is subjected to duobinary shaping, whereupon the zero substitution part is detected for removal by utilizing the rules of the zero substitution process and the alternate mark inversion signal.

摘要翻译： 一种二电平交替标记反转信号传输系统，其中将“1”和“0”电平的二进制脉冲转换为脉冲信号，其中一个编码信息值的极性在周期T被反转，另一个的极性反转为 周期T / 2，并且转换的信号被发送。 为了便于自动增益控制操作，并且即使当在发送侧处理的信号中连续出现零二进制脉冲时，系统的接收侧的定时信号的适当可靠的提取，交替标记反转信号 当零二进制脉冲彼此成功达预定次数时，转换为指定代码（零替换）信号，而在接收侧，对接收信号进行二进制整形，由此检测零替换部分以进行去除 通过利用零替换过程和替代标记反转信号的规则。

公开(公告)号：US4355398A

公开(公告)日：1982-10-19

申请号：US217339

申请日：1980-12-17

申请人： Donald M. Cook

发明人： Donald M. Cook

IPC分类号： H04L25/40 ,  H04L7/00 ,  H04L7/02 ,  H04L25/49 ,  H04L25/493

CPC分类号： H04L7/0066

摘要： This invention relates to a real time clock recovery circuit. The clock recovery circuit requires three inputs, a bit serial data received input (BSD), a quarter bit delayed (QBT) and a three quarter bit delayed (TQBT) signal. The three inputs are derived from a single raw input that becomes the received input (BSD) signal. QBT and TQBT are delay line versions of the BSD signal. The three inputs (BSD, QBT and TQBT, and the complement of these signals) are ANDed together to detect low frequencies. The generated signal indicative of the low frequency, QBT and TQBT generate a recovered clock by state sequencing of an R-S latch. The type of bit serial data stream which may be inputted to the circuit of the present invention is double frequency encoded data streams, including Manchester or diphase encoded.

摘要翻译： 本发明涉及实时时钟恢复电路。 时钟恢复电路需要三个输入，比特串行数据接收输入（BSD），四分之一比特延迟（QBT）和三分之三比特延迟（TQBT）信号。 三个输入源自成为接收输入（BSD）信号的单个原始输入。 QBT和TQBT是BSD信号的延迟线版本。 三个输入（BSD，QBT和TQBT以及这些信号的补码）被AND并入以检测低频。 所产生的指示低频，QBT和TQBT的信号通过R-S锁存器的状态排序产生恢复的时钟。 可以输入到本发明的电路的位串行数据流的类型是双频编码数据流，包括曼彻斯特或双相编码。

公开(公告)号：US4213007A

公开(公告)日：1980-07-15

申请号：US940568

申请日：1978-09-08

申请人： Gerhard Funk

发明人： Gerhard Funk

IPC分类号： H04L1/20 ,  H04L12/26 ,  H04L25/04 ,  H04L25/493 ,  H04B3/36

CPC分类号： H04L1/248 ,  H04L1/20 ,  H04L25/493

摘要： An apparatus and method for monitoring the received pulses of a transmitted pulse code modulation signal to determine if the received pulses lie within a predetermined pulse distortion tolerance zone is disclosed. The received pulses are monitored to determine the number of received pulse edges which are received during first and second consecutive predetermined time zones, the total period of the time zones being equal to the period of the pulse pattern of the received message which would occur in the case of distortionless transmission. The first time zone extends around the position where the pulse edge of the received pulses would be in the case of distortionless transmission. An error recognition signal is generated when either more than one of the received pulse edges arrives during the first time zone or only one of the received pulse edges arrives during the second time zone.

摘要翻译： 公开了一种用于监视所发送的脉冲编码调制信号的接收脉冲以确定接收到的脉冲是否在预定的脉冲失真公差区内的装置和方法。 监视所接收的脉冲以确定在第一和第二连续的预定时区期间接收到的接收到的脉冲边缘的数量，时区的总周期等于在接收到的消息中将发生的接收消息的脉冲模式的周期 无失真传输的情况。 在无失真传输的情况下，第一时区围绕接收脉冲的脉冲边缘的位置延伸。 当在第一时间段期间接收到的脉冲边缘中的一个以上到达时，或者在第二时间段期间仅接收到的一个脉冲边缘到达时，产生错误识别信号。

公开(公告)号：US4071705A

公开(公告)日：1978-01-31

申请号：US107591

申请日：1961-05-03

申请人： Ralph H. Miller, Jr. ,  William W. Dyer ,  John A. Waterbury ,  Wayland A. Carlson ,  Richard O. Eastman

发明人： Ralph H. Miller, Jr. ,  William W. Dyer ,  John A. Waterbury ,  Wayland A. Carlson ,  Richard O. Eastman

IPC分类号： H04J3/16 ,  H04L25/40 ,  H04L25/493 ,  H04J3/00

CPC分类号： H04J3/1676 ,  H04L25/40 ,  H04L25/493

摘要： 1. A quantized nonsynchronous clipped speech multi-channel coded communicons network comprising a multiplicity of transmitter terminals and receiver terminals; each of said transmitter terminals comprising a multiplicity of audio processing sections, including input means for coupling a composite waveform thereto, pre-emphasis means for generating crossover points corresponding to amplitude excursions in the input composite waveform, clipper means operatively receiving the output of said pre-emphasis means for infinitely clipping the composite waveform thereby removing the amplitude portion and leaving the frequency information, pulse generating means operatively coupled to the output of said clipper means and receiving the output of said clipper means for generating output pulses corresponding to the zero crossover points in the infinitely clipped waveform; a multiplicity of encoding sections corresponding to the audio processing sections, including gate generator means operatively receiving the output of said pulse generating means for generating gate pulses corresponding to said output pulses; a timing unit including, OR circuit means operatively coupled to said gate generating means and receiving pulses therefrom, sampling means for generating pulses corresponding to a desired sampling rate, coincidence means operatively coupled to the output of said sampling means and said OR circuit means for generating an output pulse when pulses from said OR circuit means and said sampling means coincide therein, channel coding means comprising a delay line operatively receiving output pulses from said coincidence means for generating a start stop and channel pulses corresponding to desired channel codes; second coincidence circuit means in said channel unit operatively coupled to said channel coding means and said gate generating means for generating an output pulse when pulses from said gate generating means and said channel coding means coincide therein; and transmitting means operatively coupled to said channel coder means and said second coincident circuit means for receiving start stop pulses from said channel coding means and output pulses from said second coincidence circuit means corresponding to channel codes and propagating pulse trains therefrom; each of said receiver terminals comprising; receiver means for receiving and detecting trains of pulses; channel decoder means for receiving said detected pulse trains, a multiplicity of channel coincidence means operatively coupled to the output of said channel decoder means for generating an output pulse when start stop and channel pulses are coincident therein; audio restorer means corresponding to said channel coincidence means including, flip-flop means operatively receiving output pulses from said channel coincidence means for generating a substantially square waveform in the output thereof, and integrator means receiving the output of said flip-flop and producing a waveform therefrom approximating said original composite waveform.

公开(公告)号：US4002833A

公开(公告)日：1977-01-11

申请号：US534972

申请日：1974-12-20

申请人： Joseph J. Eachus

发明人： Joseph J. Eachus

IPC分类号： H04L25/02 ,  G06F13/00 ,  H04L25/32 ,  H04L25/38 ,  H04L25/493 ,  H04L27/00

CPC分类号： H04L25/493

摘要： A method is disclosed wherein information can be conveyed serially over a signal path in a rate-independent fashion. Three or more signal states are employed for conveying information. The disclosed method consists of attaching meanings to changes of signalling state rather than the length of time that a state is maintained. It is only required that the data source and data sink establish meanings for each change of state and that each transmitted state be maintained long enough for the receiver to detect it.

摘要翻译： 公开了一种方法，其中可以以速率独立的方式通过信号路径串行地传送信息。 采用三个或更多个信号状态来传送信息。 所公开的方法包括将意义附加到信令状态的改变而不是维持状态的时间长度。 只需要数据源和数据接收器为每个状态改变建立含义，并且每个发送状态保持足够长的时间，以使接收机能够检测它。

公开(公告)号：US3816645A

公开(公告)日：1974-06-11

申请号：US32077273

申请日：1973-01-03

申请人： CONTROL DATA CORP

发明人： EHRICH W ,  BIGHAM J

IPC分类号： H04L25/493 ,  H04L15/00 ,  H04Q1/00

CPC分类号： H04L25/493

摘要： A processor substation for a communication system includes interrupt circuitry for transmitting coded communications as logic levels, rather than fixed length bits, so that communications can be handled at various code speeds and bit lengths. A message to be received by a subscriber is processed by an interrupt means in the substation to change the signal level to the subscriber whenever a transition occurs in the message (e.g. 1 to 0, and vice versa).

公开(公告)号：US3627946A

公开(公告)日：1971-12-14

申请号：US3627946D

申请日：1969-07-08

申请人： NIPPON TELEGRAPH & TELEPHONE

发明人： INOUE NOBUO ,  SATO YUICHI

IPC分类号： H03M7/00 ,  H04J3/06 ,  H04L5/22 ,  H04L5/24 ,  H04L25/493 ,  H04B1/04 ,  H03K13/00 ,  H04B1/16

CPC分类号： H04L25/493 ,  H04J3/06 ,  H04L5/225 ,  H04L5/24

摘要： In transmitting a digital signal, e.g. a digital signal on a PCM transmission line which is asynchronous with a clock signal, a first and a second state pulse trains respectively corresponding to one of the binary states of the digital signal are utilized and the output pulse trains of the asynchronous digital signal are represented by corresponding mode pulse trains in respective time slots. When the state of the pulse train of the asynchronous digital signal changes an indicating pulse representing the time of transition of the state of the asynchronous digital signal is inserted in a time slot following the time slot in which the state has changed. On the receiving terminal the mode pulse trains are constructed by utilizing the framing pulse as the reference signal.