Systems and methods for aligning received data

    公开(公告)号:US10756880B2

    公开(公告)日:2020-08-25

    申请号:US16448912

    申请日:2019-06-21

    申请人: Intel Corporation

    摘要: The present application is directed to an electronic device that has a receiver configured to receive data from a second electronic device and identify potential sync header locations within a portion of the data by performing a mutually exclusive or (XOR) logic operation on a plurality of sequential pairs of bits of the data. Additionally, the receiver is configured to identify sync headers in the data by determining which of the potential sync header locations is shared in subsequent portions of the data.

    BIT SLICER CIRCUIT FOR S-FSK RECEIVER, INTEGRATED CIRCUIT, AND METHOD ASSOCIATED THEREWITH

    公开(公告)号:US20200259687A1

    公开(公告)日:2020-08-13

    申请号:US16515248

    申请日:2019-07-18

    IPC分类号: H04L27/14 H04B1/69 H04L27/06

    摘要: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

    System and method for decoding overlapping wireless frames

    公开(公告)号:US10687186B1

    公开(公告)日:2020-06-16

    申请号:US16564417

    申请日:2019-09-09

    摘要: A processor-implemented method by a message recipient in a vehicle or on a mobile device for decoding overlapping wireless messages is provided. The method comprises: receiving a first message from a first message sender that overlaps with a second message received from a second message sender; estimating, in a first signal recovery phase, a received data symbol (d0) from the first message and a channel impulse response (h1) corresponding to a data channel between the message recipient and the second message sender; estimating, in a second signal recovery phase, a received data symbol (d0)′ from the first message and a received data symbol (d1) from the second message; and reconstructing the first message from the estimated data symbol (d0) estimated in the first signal recovery phase and estimated data symbol (d0)′ estimated during the second signal recovery phase and reconstructing the second message from the estimated data symbol (d1) estimated during the second signal recovery phase.

    PAM-4 DFE ARCHITECTURES WITH SYMBOL-TRANSITION DEPENDENT DFE TAP VALUES

    公开(公告)号:US20200153468A1

    公开(公告)日:2020-05-14

    申请号:US16680859

    申请日:2019-11-12

    申请人: Rambus Inc.

    摘要: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

    METHOD FOR RECEIVING FRAME IN WIRELESS LAN SYSTEM, AND WIRELESS TERMINAL USING SAME

    公开(公告)号:US20200092815A1

    公开(公告)日:2020-03-19

    申请号:US16618788

    申请日:2018-05-31

    IPC分类号: H04W52/02 H04L27/06 H04L5/00

    摘要: A method for receiving a frame in a wireless LAN system according to the present embodiment comprises the steps of: receiving transmission speed information according to a transmission type of a wakeup packet for a WUR module from a second wireless terminal by a first wireless terminal including a main radio module and the WUR module, wherein the transmission speed information is set on the basis of at least three transmission speeds for the wakeup packet, and the transmission speed information is received on the basis of the main radio module; and receiving the wakeup packet on the basis of the transmission speed information from the second wireless terminal by the first wireless terminal, wherein a header of the wakeup packet includes a transmission type indicator for the transmission type of the wakeup packet, the wakeup packet is modulated according to an on-off keying (OOK) scheme, and the wakeup packet is received on the basis of the WUR module.

    Method for Limiting the Level of a Modulated Signal Received by a Tag and Corresponding Limiter

    公开(公告)号:US20190385036A1

    公开(公告)日:2019-12-19

    申请号:US16442811

    申请日:2019-06-17

    IPC分类号: G06K19/07 H04L27/06 H02H9/04

    摘要: An integrated circuit, includes: an input configured to receive an induced signal that is modulated according to a protocol belonging to the group including protocols using ASK modulation and protocols using OOK modulation; a detection circuit configured to detect the modulation of the induced signal; a decoding circuit configured to detect the protocol; a configurable limiter configured to limit a level of the induced signal and having a first configuration adapted to protocols using ASK modulation and a second configuration adapted to protocols using OOK modulation; and a control circuit configured to set the limiter in the first configuration until a protocol is detected, and to switch the limiter from the first configuration to the second configuration in response to a protocol using OOK modulation being detected.