公开(公告)号：US11166380B1

公开(公告)日：2021-11-02

申请号：US17072474

申请日：2020-10-16

申请人： TactoTek Oy

发明人： Tomi Simula ,  Mika Paani ,  Miikka Kärnä ,  Outi Rusanen ,  Johanna Juvani ,  Tapio Rautio ,  Marko Suo-Anttila ,  Mikko Heikkinen

IPC分类号： H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/08 ,  H05K3/12 ,  H05K3/28 ,  H05K3/32 ,  H05K3/44 ,  H01L21/00 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/77 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/16 ,  H01L23/18 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/552 ,  H01L23/538 ,  H05K5/03 ,  B29C45/14 ,  H05K5/06 ,  B29K101/12 ,  B29L31/34

摘要： A structure includes a first substrate film and a functional electronics assembly. The first substrate film comprises a recess defining a volume. The functional electronics assembly comprises at least a first substrate, at least one electronics component on the first substrate, and at least one connection portion. The functional electronics assembly is connected to the first substrate film via the at least one connection portion. The at least one electronics component is arranged at least partly into the volume. At least part of the at least one electronics component is embedded into a first material arranged into the recess.

公开(公告)号：US20210335756A1

公开(公告)日：2021-10-28

申请号：US17369119

申请日：2021-07-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinkyeong Seol ,  Sunchul Kim ,  Pyoungwan Kim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/16 ,  H01L23/31

摘要： A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

公开(公告)号：US11139253B2

公开(公告)日：2021-10-05

申请号：US16583335

申请日：2019-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Chui Woo Kim ,  Sang Min Yong ,  Yang Gyoo Jung

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L25/065

摘要： A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

公开(公告)号：US11107769B2

公开(公告)日：2021-08-31

申请号：US16845890

申请日：2020-04-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jongho Park ,  Seung Hwan Kim ,  Jun Young Oh ,  Kyong Hwan Koh ,  Sangsoo Kim ,  Dong-Ju Jang

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/16 ,  H01L25/065

摘要： A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

公开(公告)号：US11107701B2

公开(公告)日：2021-08-31

申请号：US16740770

申请日：2020-01-13

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Jin Young Kim ,  Doo Hyun Park ,  Seung Jae Lee

IPC分类号： H01L21/48 ,  H01L23/31 ,  H01L23/16 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

摘要： A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

公开(公告)号：US11088091B2

公开(公告)日：2021-08-10

申请号：US16866988

申请日：2020-05-05

申请人： Samsung Electronics Co., Ltd.

发明人： Su Chang Lee

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L23/16 ,  H01L23/29

摘要： A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip.

公开(公告)号：US20210225729A1

公开(公告)日：2021-07-22

申请号：US16746732

申请日：2020-01-17

申请人： Intel Corporation

发明人： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC分类号： H01L23/373 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48

摘要： A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

公开(公告)号：US20210217682A1

公开(公告)日：2021-07-15

申请号：US17219909

申请日：2021-04-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Chia Chiu ,  Li-Han Hsu

IPC分类号： H01L23/40 ,  H01L23/31 ,  H01L23/04 ,  H01L23/16

摘要： A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

公开(公告)号：US20210166949A1

公开(公告)日：2021-06-03

申请号：US17108471

申请日：2020-12-01

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics (Malta) Ltd

发明人： Roseanne DUCA ,  Dario PACI ,  Pierpaolo RECANATINI

IPC分类号： H01L21/324 ,  H01L23/16 ,  H01L23/31

摘要： A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

公开(公告)号：US20210159180A1

公开(公告)日：2021-05-27

申请号：US17166795

申请日：2021-02-03

申请人： Apple Inc.

发明人： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/16 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

摘要： Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.