公开(公告)号：US11145672B2

公开(公告)日：2021-10-12

申请号：US16706684

申请日：2019-12-07

申请人： Samsung Electronics Co., Ltd.

发明人： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC分类号： H01L27/11582 ,  H01L23/00 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11531

摘要： A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US20210305270A1

公开(公告)日：2021-09-30

申请号：US17085715

申请日：2020-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Dawoon JEONG ,  Youngwoo KIM ,  Jaesung KIM ,  Hyoungryeol IN

IPC分类号： H01L27/11575 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11548

摘要： A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate in the first region and extending in different lengths along a second direction, perpendicular to the first direction in the second region, first separation regions penetrating the gate electrodes in the first and second regions, extending in the second direction, and spaced apart from each other in a third direction, perpendicular to the first and second directions, second separation regions penetrating the gate electrodes in the second region and spaced apart from each other in the second direction between the separation regions, and a first vertical structure penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation regions in the third direction is greater than a width of the first vertical structure, a first end point of the second separation regions adjacent to the first region is spaced apart from a central axis of the first dummy structure in the second direction, away from the first region.

公开(公告)号：US20210296355A1

公开(公告)日：2021-09-23

申请号：US17010751

申请日：2020-09-02

申请人： KIOXIA CORPORATION

发明人： Shun MATSUOKA

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/265

摘要： According to one embodiment, a semiconductor storage device includes a first structural body on a semiconductor material. The first structural body having a plurality of first conductive films and a plurality of first insulating films that are alternately stacked. A first columnar body penetrates the first structural body and includes a first epitaxial layer on an end adjacent to the semiconductor material. A second columnar body also penetrates the first structural body and includes a second epitaxial layer on an end adjacent to the semiconductor material. A portion of the second epitaxial layer is doped with boron.

公开(公告)号：US20210288068A1

公开(公告)日：2021-09-16

申请号：US17034420

申请日：2020-09-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ga Eun KIM ,  Yoon Hwan SON ,  Sung Won CHO ,  Joo Hee PARK

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  G11C16/24 ,  G11C16/08

摘要： A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.

公开(公告)号：US11121153B1

公开(公告)日：2021-09-14

申请号：US16800097

申请日：2020-02-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： Tomoyuki Obu ,  Shinsuke Yada

IPC分类号： H01L21/00 ,  H01L27/11582 ,  H01L29/66 ,  H01L27/11519 ,  H01L29/10 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/417

摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. A layer stack including a charge storage layer, a tunneling dielectric layer, a semiconductor material layer, and a dielectric material layer is formed in the memory openings. The dielectric material layer may include a doped silicate glass layer. A doped silicate glass pillar can be formed at a bottom portion of each memory opening, and a bottom portion of the semiconductor material layer can be converted into a source region by outdiffusion of dopants from the doped silicate glass pillar. Alternatively, the semiconductor material layer can be heavily doped, and can be recessed to form a source region.

公开(公告)号：US11114463B2

公开(公告)日：2021-09-07

申请号：US16892384

申请日：2020-06-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung Jun Shin ,  Hyun Mog Park ,  Joong Shik Shin

IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/788 ,  H01L27/1157

摘要： A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20210272977A1

公开(公告)日：2021-09-02

申请号：US17018062

申请日：2020-09-11

申请人： Kioxia Corporation

发明人： Kojiro SHIMIZU

IPC分类号： H01L27/11575 ,  H01L27/11565 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

公开(公告)号：US11107765B2

公开(公告)日：2021-08-31

申请号：US16853850

申请日：2020-04-21

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US11081492B2

公开(公告)日：2021-08-03

申请号：US16857647

申请日：2020-04-24

申请人： Toshiba Memory Corporation

发明人： Tetsuaki Utsumi

IPC分类号： H01L27/11568 ,  H01L27/11582 ,  H01L25/065 ,  G11C5/04 ,  H01L23/00 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/822 ,  H01L21/28 ,  G11C29/02 ,  H01L27/11573 ,  H01L27/11575 ,  G11C29/04

摘要： A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

公开(公告)号：US11069706B2

公开(公告)日：2021-07-20

申请号：US16573695

申请日：2019-09-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11556

摘要： In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.