Clock synchronization NIC offload
    611.
    发明授权

    公开(公告)号:US12255734B2

    公开(公告)日:2025-03-18

    申请号:US17973575

    申请日:2022-10-26

    Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.

    Transparent recovery of emulated storage device after a failure

    公开(公告)号:US12248372B2

    公开(公告)日:2025-03-11

    申请号:US18186171

    申请日:2023-03-19

    Abstract: In one embodiment, a system includes a storage device controller including a first controller to read commands from a submission queue stored in a shared memory, provide the commands to a second controller, and write completion notices received from the second controller to a completion queue in the shared memory, and the second controller to receive the commands from the first controller, perform storage operations with a non-volatile memory responsively to receiving the commands, generate the completion notices responsively to performing the storage operations, provide the completion notices to the first controller, write recovery data about the commands and the completion notices to a persistent memory, and recover from a failure responsively to retrieving the recovery data from the persistent memory.

    Systems and methods of initiating retransmission requests

    公开(公告)号:US12244416B2

    公开(公告)日:2025-03-04

    申请号:US18192239

    申请日:2023-03-29

    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.

    Efficient and flexible flow inspector

    公开(公告)号:US12231401B2

    公开(公告)日:2025-02-18

    申请号:US17714207

    申请日:2022-04-06

    Abstract: In one embodiment, a data communication device includes a network interface controller to process packets received from at least one of a host device for sending over a network, and at least one remote device over the network, at least one processor to execute computer instructions to receive a configuration, and extract filtering rules from the configuration, and at least one hardware accelerator to receive the filtering rules from the at least one processor, and filter the packets based on the rules so that some of the packets are dropped and some of the packets are forwarded to the at least one processor to send data based on the forwarded packets to another device.

    Systems, methods, and apparatuses for securing ownership of objects in a digital ledger

    公开(公告)号:US12229296B2

    公开(公告)日:2025-02-18

    申请号:US17863779

    申请日:2022-07-13

    Abstract: Various embodiments of the present disclosure provide for generating and managing a digital ledger access system and its associated objects. An example method is configured for securing objects in a digital ledger of objects by identifying an object from amongst a plurality of objects in the digital ledger of objects and generating a quantum token for attachment with the object. The method includes deriving one or more classical public keys associated with the quantum token and determining an attempt to access the object. The method provides access to the object in response to a validation of the classical public key based on the quantum token, and the method precludes access to the object in response to an invalidation of the classical public key based on the quantum token.

    Wafer level analysis for VCSEL screening

    公开(公告)号:US12224550B2

    公开(公告)日:2025-02-11

    申请号:US17156902

    申请日:2021-01-25

    Abstract: A method and system for analyzing Vertical-Cavity Surface-Emitting Lasers (VCSELs) on a wafer are provided. An illustrative method of is provided that includes: applying a stimulus to each of the plurality of VCSELs on the wafer; measuring, for each of the plurality of VCSELs, two or more VCSEL parameters responsive to the stimulus; correlating the measured two or more VCSEL parameters to define a value of a common performance characteristic; and identifying clusters of VCSELs having similar values of the common performance characteristic. The clusters of VCSELs may be determined to collectively meet or not meet an optical performance requirement defined for the VCSELs on the wafer.

    Synchronization of LED Indications
    620.
    发明申请

    公开(公告)号:US20250048519A1

    公开(公告)日:2025-02-06

    申请号:US18361970

    申请日:2023-07-31

    Abstract: A network device includes a plurality of ports, a plurality of optical indicators, two or more packet processing circuits, and synchronization circuitry. The two or more packet processing circuits are to process packets communicated over the ports, each packet processing circuit to control a subset of the optical indicators to display status information relating to a subset of the ports. At least some of the status information is represented by blinking of the optical indicators. The synchronization circuitry is to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits.

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