公开(公告)号：US10475799B2

公开(公告)日：2019-11-12

申请号：US15901875

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US10475708B2

公开(公告)日：2019-11-12

申请号：US16299395

申请日：2019-03-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yong-Liang Li ,  Hao Su

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

公开(公告)号：US20190341252A1

公开(公告)日：2019-11-07

申请号：US15968680

申请日：2018-05-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US10468538B1

公开(公告)日：2019-11-05

申请号：US16038068

申请日：2018-07-17

Applicant: United Microelectronics Corp.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L27/11517 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

公开(公告)号：US10465287B2

公开(公告)日：2019-11-05

申请号：US15919191

申请日：2018-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: C23C16/455 ,  H01L21/768 ,  H01L23/544 ,  H01L21/285 ,  H01L21/321 ,  C23C16/02 ,  C23C16/34

Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.

公开(公告)号：US10460925B2

公开(公告)日：2019-10-29

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US10453677B2

公开(公告)日：2019-10-22

申请号：US15644821

申请日：2017-07-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Cheng-Hsu Huang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/108

Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.

公开(公告)号：US20190318930A1

公开(公告)日：2019-10-17

申请号：US15975730

申请日：2018-05-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Hsin-Yu Chiang

IPC: H01L21/033 ,  H01L21/311

Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.

公开(公告)号：US10446689B1

公开(公告)日：2019-10-15

申请号：US16274190

申请日：2019-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/768 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4757 ,  H01L29/786

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US10446688B1

公开(公告)日：2019-10-15

申请号：US16190090

申请日：2018-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.