公开(公告)号：US10515976B2

公开(公告)日：2019-12-24

申请号：US15885878

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Tzu-Ping Chen

IPC: H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

公开(公告)号：US20160049413A1

公开(公告)日：2016-02-18

申请号：US14489439

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L27/115 ,  H01L29/66 ,  G11C16/14 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  H01L29/40

CPC classification number: H01L29/7887 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 衬底上的浮动栅极; 在浮置栅极和衬底之间的第一氧化硅层; 与第一氧化硅层的两侧相邻的第一隧道氧化物层和第二隧道氧化物层; 和浮动门上的控制门。 优选地，第一隧道氧化物层和第二隧道氧化物层的厚度小于第一氧化硅层的厚度。

公开(公告)号：US11018132B2

公开(公告)日：2021-05-25

申请号：US16380953

申请日：2019-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L27/06 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11541 ,  H01L27/11543 ,  H01L21/311 ,  H01L21/285

Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate.

公开(公告)号：US20150008504A1

公开(公告)日：2015-01-08

申请号：US13935570

申请日：2013-07-05

Applicant: United Microelectronics Corp.

Inventor： Chun-Lung Chang ,  Tzu-Ping Chen ,  Chih-Haw Lee ,  Kuan-Yi Tseng ,  Chih-Jung Chen ,  Chien-Hung Chen

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7923

Abstract: A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer.

Abstract translation: 非易失性存储器结构包括：衬底，形成在衬底上的栅极电极，分别形成在栅电极的两侧上的导电衬垫和在衬底上形成有倒T形的氧化物 - 氧化物（ONO）结构 。 栅电极包括栅极导电层和栅极电介质层。 ONO结构包括基部和主体部分。 ONO结构的基部被夹在栅电极和衬底之间以及导电间隔物和衬底之间。 T形ONO结构的主体部分从基部向上延伸并夹在栅电极和导电间隔件之间。

公开(公告)号：US11437475B2

公开(公告)日：2022-09-06

申请号：US17178269

申请日：2021-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L21/28 ,  H01L29/788 ,  H01L21/32 ,  H01L21/321 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311

Abstract: A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

公开(公告)号：US10903224B2

公开(公告)日：2021-01-26

申请号：US16685130

申请日：2019-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Tzu-Ping Chen

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

公开(公告)号：US10332964B2

公开(公告)日：2019-06-25

申请号：US15352587

申请日：2016-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11558

Abstract: A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

公开(公告)号：US09773800B1

公开(公告)日：2017-09-26

申请号：US15250930

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L21/336 ,  H01L29/792 ,  H01L31/119 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.

公开(公告)号：US09171915B1

公开(公告)日：2015-10-27

申请号：US14277784

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen

IPC: H01L21/336 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L29/401 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：首先提供衬底，其中衬底包括SONOS区域和EEPROM区域。 接下来，在SONOS区域和EEPROM区域中形成第一栅极层，通过从SONOS区域移除第一栅极层并在EEPROM区域中形成浮置栅极图案来对第一栅极层进行图案化，形成ONO层 SONOS区域和EEPROM区域，在SONOS区域的ONO层上形成第二栅极层，对EEPROM区域，第二栅极层和第一栅极层进行图案化以在EEPROM中形成浮置栅极和控制栅极 区域，并且第二栅极层被图案化以在SONOS区域中形成第一栅极。

公开(公告)号：US20250120087A1

公开(公告)日：2025-04-10

申请号：US18502091

申请日：2023-11-06

Applicant: United Microelectronics Corp.

Inventor： Jen Yang Hsueh ,  Chien-Hung Chen ,  Tzu-Ping Chen ,  Chia-Hui Huang ,  Chia-Wen Wang ,  Chih-Yang Hsu ,  Ling Hsiu Chou

IPC: H10B43/30 ,  H10B41/30

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.