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    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    非易失性存储器结构及其制造方法

    公开(公告)号：US20150008504A1

    公开(公告)日：2015-01-08

    申请号：US13935570

    申请日：2013-07-05

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Lung Chang ,  Tzu-Ping Chen ,  Chih-Haw Lee ,  Kuan-Yi Tseng ,  Chih-Jung Chen ,  Chien-Hung Chen

    IPC: H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7923

    Abstract: A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer.

    Abstract translation: 非易失性存储器结构包括：衬底，形成在衬底上的栅极电极，分别形成在栅电极的两侧上的导电衬垫和在衬底上形成有倒T形的氧化物 - 氧化物（ONO）结构 。 栅电极包括栅极导电层和栅极电介质层。 ONO结构包括基部和主体部分。 ONO结构的基部被夹在栅电极和衬底之间以及导电间隔物和衬底之间。 T形ONO结构的主体部分从基部向上延伸并夹在栅电极和导电间隔件之间。

    Split-gate flash memory cell and fabrication method thereof
    3.
    发明授权
    Split-gate flash memory cell and fabrication method thereof 有权

    公开(公告)号：US11437475B2

    公开(公告)日：2022-09-06

    申请号：US17178269

    申请日：2021-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

    IPC: H01L21/28 ,  H01L29/788 ,  H01L21/32 ,  H01L21/321 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311

    Abstract: A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

    Single poly electrical erasable programmable read only memory (EEPROM)
    4.
    发明授权
    Single poly electrical erasable programmable read only memory (EEPROM) 有权

    公开(公告)号：US10332964B2

    公开(公告)日：2019-06-25

    申请号：US15352587

    申请日：2016-11-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11558

    Abstract: A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

    SPLIT-GATE FLASH MEMORY CELL AND FABRICATION METHOD THEREOF
    5.
    发明申请
    SPLIT-GATE FLASH MEMORY CELL AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20220216311A1

    公开(公告)日：2022-07-07

    申请号：US17178269

    申请日：2021-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

    IPC: H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/66

    Abstract: A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

    Method for fabricating semiconductor device
    6.
    发明授权
    Method for fabricating semiconductor device 有权

    公开(公告)号：US10468538B1

    公开(公告)日：2019-11-05

    申请号：US16038068

    申请日：2018-07-17

    Applicant: United Microelectronics Corp.

    Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

    IPC: H01L29/788 ,  H01L27/11517 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

    Abstract: A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

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