公开(公告)号：US20240211578A1

公开(公告)日：2024-06-27

申请号：US18391185

申请日：2023-12-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  PROTON WORLD INTERNATIONAL N.V.

Inventor： Olivier VAN NIEUWENHUYZE ,  Alexandre CHARLES

IPC: G06F21/44

CPC classification number: G06F21/44

Abstract: An electronic device includes a secure element and an application programming interface. The secure element, in operation, executes a first application. The application programming interface, in operation, verifies a reliability of a received command directed to the first application, and transmits the command and a result of the verification to the first application.

公开(公告)号：US20240186236A1

公开(公告)日：2024-06-06

申请号：US18437720

申请日：2024-02-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L23/522 ,  H01L21/762 ,  H01L27/08 ,  H01L29/66

CPC classification number: H01L23/5223 ,  H01L21/76224 ,  H01L27/0805 ,  H01L29/66181

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US12004432B2

公开(公告)日：2024-06-04

申请号：US17507645

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Roberto Simola ,  Yohann Moustapha-Rabault

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US12001593B2

公开(公告)日：2024-06-04

申请号：US17199438

申请日：2021-03-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/088 ,  H03K19/17768

CPC classification number: G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/0883 ,  H03K19/17768

Abstract: An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

公开(公告)号：US20240178842A1

公开(公告)日：2024-05-30

申请号：US18435913

申请日：2024-02-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20240136351A1

公开(公告)日：2024-04-25

申请号：US18485201

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Loic BOURGUINE ,  Lionel ESTEVE

IPC: H01L27/06 ,  H01L27/088 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H01L27/0629 ,  H01L27/0886 ,  H01L29/2003 ,  H01L29/7783 ,  H01L29/7787

Abstract: The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.

公开(公告)号：US11949252B2

公开(公告)日：2024-04-02

申请号：US17571705

申请日：2022-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Anthony Tornambe ,  Nicolas Cordier

IPC: H02J50/80 ,  H02J50/40 ,  H02J50/50

CPC classification number: H02J50/80 ,  H02J50/40 ,  H02J50/50

Abstract: A contactless device includes an impedance matching and filter circuit connected to an antenna and being on the one hand operable for contactlessly communicating with a second device via the antenna, and on the other hand operable for contactlessly charging a rechargeable power supply of a third device via the antenna. A method of control includes modifying the impedance matching and filter circuit of the contactless device depending on whether the contactless device carries out the contactless communication or carries out the contactless charging.

公开(公告)号：US11943008B2

公开(公告)日：2024-03-26

申请号：US18153958

申请日：2023-01-12

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Chia Hao Chen ,  Nicolas Cordier

IPC: H04B5/00 ,  H02J50/10 ,  H02J50/80 ,  H02J50/90

CPC classification number: H04B5/0037 ,  H02J50/10 ,  H02J50/80 ,  H02J50/90 ,  H04B5/0031 ,  H04B5/0081

Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

公开(公告)号：US11942935B2

公开(公告)日：2024-03-26

申请号：US17861067

申请日：2022-07-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark Wallis ,  Jean-Francois Link ,  Joran Pantel

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20240087652A1

公开(公告)日：2024-03-14

申请号：US18243193

申请日：2023-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/16

Abstract: A nonvolatile memory device has a “split-voltage” architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors for memory cells of a memory word are gate controlled by a control element. All control elements of a same row are controlled by a first control signal generated by a first row control circuit in response to a set-reset (SR) latch output signal output for a selected row. In order to write a piece of data in a memory word, the first row control circuit confers onto the first control signal an erasing voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal without modifying, between erasing and programming the memory word, the state of the latch output signal for the selected row.