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公开(公告)号：US11914450B2
公开(公告)日：2024-02-27
申请号：US17838157
申请日：2022-06-10
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Tramoni
IPC: G06F1/32 , G06F1/3296 , G06F1/3203
CPC classification number: G06F1/3296 , G06F1/3203
Abstract: In an embodiment, an electronic device includes a first near field communication module, at least one second communication module, at least one portion of a volatile memory, at least one register, and at least one first circuit configured to activate the near field communication module, wherein the at least one second communication module is configured to power the at least one portion of the volatile memory, the at least one register and the at least one first circuit with a first supply voltage when the electronic device is in an on state and when the first near field communication module is in a standby mode.
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公开(公告)号：US20240063280A1
公开(公告)日：2024-02-22
申请号：US18230423
申请日：2023-08-04
Inventor： Franck JULIEN , Julien DELALLEAU , Julien DURA , Julien AMOUROUX , Stephane MONFRAY
IPC: H01L29/423 , H01L29/78 , H01L29/40
CPC classification number: H01L29/42376 , H01L29/7833 , H01L29/42368 , H01L29/401
Abstract: A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.
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公开(公告)号：US11906994B2
公开(公告)日：2024-02-20
申请号：US17836524
申请日：2022-06-09
Inventor： Daniele Mangano , Andrei Tudose , Francesco Clerici , Pasquale Butta'
IPC: G06F1/00 , G05F1/46 , G06F1/3296
CPC classification number: G05F1/468 , G06F1/3296
Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
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公开(公告)号：US20240040781A1
公开(公告)日：2024-02-01
申请号：US18484906
申请日：2023-10-11
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
IPC: H10B20/00
CPC classification number: H10B20/367 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L41/0803 , H04L49/109 , G06F21/85
CPC classification number: H04L49/109 , G06F21/85 , H04L41/0803
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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Patent Agency Ranking
公开(公告)号：US20240006998A1
公开(公告)日：2024-01-04
申请号：US17856657
申请日：2022-07-01
Inventor： Vanni Poletto , Antoine Pavlin
CPC classification number: H02M3/1586 , B60L53/22 , B60L58/20 , B60L2210/12 , B60L2210/14
Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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公开(公告)号：US11863248B2
公开(公告)日：2024-01-02
申请号：US18159813
申请日：2023-01-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Tramoni
IPC: H04B5/00
CPC classification number: H04B5/0031 , H04B5/0043 , H04B5/0062 , H04B5/0087
Abstract: A device includes a first circuit that includes a near-field emission circuit, a second circuit, and a hardware connection linking the first circuit to the second circuit. The hardware connection is dedicated to a priority management between the first circuit and the second circuit. In addition, priority management information can be communicated between a near-field emission circuit and a second circuit. The communicating occurs between a dedicated hardware connection connecting the near-field emission circuit to the second circuit.
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公开(公告)号：US11856080B2
公开(公告)日：2023-12-26
申请号：US18059784
申请日：2022-11-29
Inventor： Vincent Pascal Onde , Diarmuid Emslie , Patrick Valdenaire
IPC: H04L7/00
CPC classification number: H04L7/0012
Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.
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公开(公告)号：US11855713B2
公开(公告)日：2023-12-26
申请号：US17701416
申请日：2022-03-22
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Nicolas Cordier
IPC: H04B5/00 , H04B17/318
CPC classification number: H04B5/0031 , H04B17/318
Abstract: The present disclosure relates to a method implemented by a first NFC device, wherein the establishment of a transaction with a second NFC device configured in reader mode is performed when the signal level received by the first device, configured in card mode, reaches a first threshold, depending on the type of modulation technology of the second device.
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公开(公告)号：US11853765B2
公开(公告)日：2023-12-26
申请号：US17721193
申请日：2022-04-14
Inventor： Michael Peeters , Fabrice Marinet
IPC: G06F9/30
CPC classification number: G06F9/30185 , G06F9/30134 , G06F9/30145 , G06F9/30105
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
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