公开(公告)号：US09117749B1

公开(公告)日：2015-08-25

申请号：US13836080

申请日：2013-03-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/24 ,  H01L27/108 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L27/2436 ,  G11C8/16 ,  H01L24/13 ,  H01L24/16 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1108 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/228 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device, including: a first transistor sharing a first diffusion with a second transistor; a third transistor sharing a second diffusion with the second transistor; and at least one programmable resistor; wherein the at least one programmable resistor is connected to the first diffusion and the second diffusion, wherein the at least one programmable resistor includes one of the following: memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

Abstract translation: 一种半导体器件，包括：与第二晶体管共享第一扩散的第一晶体管; 与所述第二晶体管共享第二扩散的第三晶体管; 和至少一个可编程电阻器; 其中所述至少一个可编程电阻器连接到所述第一扩散层和所述第二扩散层，其中所述至少一个可编程电阻器包括以下之一：忆阻器，过渡金属氧化物，聚合物忆阻器，铁电忆阻器，自旋电子忆阻器， 相变结构，可编程金属化结构，导电桥接结构，磁阻结构，硫族化物结构。

公开(公告)号：US20150069523A1

公开(公告)日：2015-03-12

申请号：US14541452

申请日：2014-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive structure underneath at least one of the second single crystal transistors, the at least one conductive structure is constructed to provide a back-bias to at least one of the second single crystal transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及在所述第二单晶体晶体管中的至少一个下方的至少一个导电结构，所述至少一个导电结构被构造为向所述第二单晶体晶体管中的至少一个提供反偏压。

公开(公告)号：US08902663B1

公开(公告)日：2014-12-02

申请号：US13792202

申请日：2013-03-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: G11C16/04 ,  G11C16/02

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell, the method including: applying a back-bias to the first cell and the second cell without interrupting data access to the memory, and generating at least two stable floating body charge levels of the memory state.

Abstract translation: 一种保持3D存储器的存储状态的方法，其中所述存储器至少包括第一单元和覆盖所述第一单元的第二单元，所述方法包括：将第一单元和所述第二单元的反向偏压应用于中断数据 访问存储器，并且产生存储器状态的至少两个稳定的浮动体电荷电平。

公开(公告)号：US08803206B1

公开(公告)日：2014-08-12

申请号：US13855786

申请日：2013-04-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Abstract translation: 一种3D半导体器件，包括：第一层，包括第一晶体管; 包括第二晶体管的第二层; 其中第二晶体管与第一晶体管对准，以及第一电路，其包括第一晶体管中的至少一个，其中第一电路具有连接到至少一个第二晶体管的第一电路输出，并且其中至少一个 第二晶体管连接到器件输出，并且其中器件输出包括用于连接到外部器件的接触端口，并且其中第二晶体管中的至少一个基本上大于第一晶体管中的至少一个。

公开(公告)号：US08742476B1

公开(公告)日：2014-06-03

申请号：US13685751

申请日：2012-11-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/336 ,  H01L21/477

CPC classification number: H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract translation: 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上并且包括铜或铝; 和覆盖在金属层上的第二层; 第二层包括第二晶体管，其包括单晶并且与第一对准标记对准，具有小于40nm的对准误差，单晶包括相对于彼此水平取向的第一区域和第二区域， 区域具有与第二区域基本上不同的掺杂剂浓度。

公开(公告)号：US20140145272A1

公开(公告)日：2014-05-29

申请号：US13685751

申请日：2012-11-27

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L23/544 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract translation: 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上并且包括铜或铝; 和覆盖在金属层上的第二层; 第二层包括第二晶体管，其包括单晶并且与第一对准标记对准，具有小于40nm的对准误差，单晶包括相对于彼此水平取向的第一区域和第二区域， 区域具有与第二区域基本上不同的掺杂剂浓度。