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    Strained transistor integration for CMOS
    61.
    发明授权
    Strained transistor integration for CMOS 失效
    用于CMOS的应变晶体管集成

    公开(公告)号：US07662689B2

    公开(公告)日：2010-02-16

    申请号：US10747321

    申请日：2003-12-23

    Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    IPC: H01L21/8236

    CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

    Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

    Selective etch for patterning a semiconductor film deposited non-selectively
    64.
    发明授权
    Selective etch for patterning a semiconductor film deposited non-selectively 有权
    用于图案化非选择性沉积的半导体膜的选择性蚀刻

    公开(公告)号：US07517772B2

    公开(公告)日：2009-04-14

    申请号：US12034118

    申请日：2008-02-20

    Applicant: Willy Rachmady ,  Anand Murthy

    Inventor： Willy Rachmady ,  Anand Murthy

    IPC: H01L21/20

    CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

    Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

    SELECTIVE ETCH FOR PATTERNING A SEMICONDUCTOR FILM DEPOSITED NON-SELECTIVELY
    67.
    发明申请
    SELECTIVE ETCH FOR PATTERNING A SEMICONDUCTOR FILM DEPOSITED NON-SELECTIVELY 有权
    非选择性地沉积半导体膜的选择性蚀刻

    公开(公告)号：US20080153237A1

    公开(公告)日：2008-06-26

    申请号：US12034118

    申请日：2008-02-20

    Applicant: Willy Rachmady ,  Anand Murthy

    Inventor： Willy Rachmady ,  Anand Murthy

    IPC: H01L21/20 ,  H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

    Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

    Multi-component strain-inducing semiconductor regions
    68.
    发明申请
    Multi-component strain-inducing semiconductor regions 有权
    多组分应变诱导半导体区域

    公开(公告)号：US20080124878A1

    公开(公告)日：2008-05-29

    申请号：US11605739

    申请日：2006-11-28

    Applicant: Ted E. Cook ,  Bernhard Sell ,  Anand Murthy

    Inventor： Ted E. Cook ,  Bernhard Sell ,  Anand Murthy

    IPC: H01L21/336

    CPC classification number: H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

    Abstract translation: 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

    Selective deposition to improve selectivity and structures formed thereby
    69.
    发明授权
    Selective deposition to improve selectivity and structures formed thereby 有权
    选择性沉积以改善由此形成的选择性和结构

    公开(公告)号：US07358547B2

    公开(公告)日：2008-04-15

    申请号：US11152266

    申请日：2005-06-13

    Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

    Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

    IPC: H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

    CPC classification number: H01L29/66636 ,  H01L21/823418

    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

    Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

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