公开(公告)号：US20060148196A1

公开(公告)日：2006-07-06

申请号：US11028811

申请日：2005-01-03

申请人： Voon-Yew Thean ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Thien Nguyen ,  Tab Stephens

发明人： Voon-Yew Thean ,  Brian Goolsby ,  Bich-Yen Nguyen ,  Thien Nguyen ,  Tab Stephens

IPC分类号： H01L21/76

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78639

摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.

摘要翻译： 在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层 晶圆。 去除有源层的上部以形成晶体管沟道结构。 在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。 执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。 隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

公开(公告)号：US07067868B2

公开(公告)日：2006-06-27

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

公开(公告)号：US07037795B1

公开(公告)日：2006-05-02

申请号：US10965964

申请日：2004-10-15

申请人： Alexander L. Barr ,  Olubunmi O. Adetutu ,  Bich-Yen Nguyen ,  Marius K. Orlowski ,  Mariam G. Sadaka ,  Voon-Yew Thean ,  Ted R. White

发明人： Alexander L. Barr ,  Olubunmi O. Adetutu ,  Bich-Yen Nguyen ,  Marius K. Orlowski ,  Mariam G. Sadaka ,  Voon-Yew Thean ,  Ted R. White

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/78618

摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

公开(公告)号：US20060084235A1

公开(公告)日：2006-04-20

申请号：US10965964

申请日：2004-10-15

申请人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/78618

摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

公开(公告)号：US20060084207A1

公开(公告)日：2006-04-20

申请号：US10969108

申请日：2004-10-20

申请人： Ted White ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L21/338

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045

摘要： P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.

摘要翻译： P沟道晶体管形成在具有用于增强P沟道晶体管性能的（110）表面取向的半导体层中，并且N沟道晶体管形成在具有（100）表面取向的半导体层中。 为了进一步提供P沟道晶体管性能增强，它们的沟道长度的方向根据其沟道方向来选择。 窄宽度P沟道晶体管优选地在<100>方向上取向。 宽通道宽度P沟道晶体管优选地在<110>方向上取向。

公开(公告)号：US20060065927A1

公开(公告)日：2006-03-30

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US07018901B1

公开(公告)日：2006-03-28

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US20060063320A1

公开(公告)日：2006-03-23

申请号：US10949057

申请日：2004-09-23

申请人： Marius Orlowski ,  Bich-Yen Nguyen

发明人： Marius Orlowski ,  Bich-Yen Nguyen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/78642 ,  H01L29/78687

摘要： A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.

摘要翻译： 半导体制造工艺包括在半导体衬底中形成凹部。 硅锗膜形成在凹槽的侧壁上。 在硅锗膜附近形成栅极电介质和栅电极。 然后形成源极/漏极区，其中第一源极/漏极区在衬底的上表面中与栅电极的第一侧相邻，并且与栅电极的第二侧相邻的第二源极/漏极区在下表面 的凹陷。 可以对衬底的暴露部分进行蚀刻，以便在凹陷侧壁和凹陷下表面的接合处形成圆角。 硅锗膜的形成优选是外延的。 可以在硅锗膜附近形成外延硅膜。

公开(公告)号：US20050101069A1

公开(公告)日：2005-05-12

申请号：US10695163

申请日：2003-10-28

申请人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

发明人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

公开(公告)号：US06838322B2

公开(公告)日：2005-01-04

申请号：US10427577

申请日：2003-05-01

申请人： Daniel T. Pham ,  Alexander L. Barr ,  Leo Mathew ,  Bich-Yen Nguyen ,  Anne M. Vandooren ,  Ted R. White

发明人： Daniel T. Pham ,  Alexander L. Barr ,  Leo Mathew ,  Bich-Yen Nguyen ,  Anne M. Vandooren ,  Ted R. White

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/20 ,  H01L21/3205

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).

摘要翻译： 一种用于形成多晶硅FinFET（10）或其它薄膜晶体管结构的方法包括在半导体衬底（14）上形成绝缘层（12）。 在绝缘层（12）上形成非晶硅层（32）。 与用于控制硅晶粒生长的非晶硅层（32）相关联地形成硅锗籽晶层（44）。 多晶硅层由退火非晶硅层（32）引起。 在退火步骤期间，硅锗籽晶层（44）与硅锗层（34）一起催化硅重结晶以促进生长较大的晶粒以及所得多晶硅层内的较少的晶界。 源极（16），漏极（18）和沟道（20）区域形成在多晶硅层内。 与源极（16），漏极（18）和沟道（20）相关联地形成双门控区域（24）以产生多晶硅FinFET（10）。