公开(公告)号：US07889555B2

公开(公告)日：2011-02-15

申请号：US11764613

申请日：2007-06-18

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US07672170B2

公开(公告)日：2010-03-02

申请号：US11769429

申请日：2007-06-27

Applicant: Byeong-Hoon Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Sun-Kwon Kim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/3454

Abstract: A method for programming a flash memory device with a plurality of memory cells. A selected memory cell is programmed under a condition where a bulk area is biased with a high voltage. A program pass/fail of the memory cell is verified with the high voltage applied to the bulk area.

Abstract translation: 一种用于对具有多个存储器单元的闪存器件进行编程的方法。 选择的存储单元在大块区域被高电压偏置的条件下被编程。 存储单元的程序通过/失败通过施加到体积区域的高电压来验证。

公开(公告)号：US07493484B2

公开(公告)日：2009-02-17

申请号：US11050477

申请日：2005-02-03

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G06F9/00 ,  G06F11/00

CPC classification number: G06F9/4401 ,  G06F8/654 ,  G06F8/66

Abstract: A memory system and corresponding method for executing boot code stored therein are provided, the memory system including a mode decoder, a first memory in signal communication with the mode decoder, a second memory in signal communication with the mode decoder, and a mode generator in signal communication with the mode decoder for generating a signal indicative of selecting one of the first and second memories as the boot memory; and the method for executing boot code including initially booting the system from a first memory, programming a second memory for subsequent booting, programming a mode generator to subsequently boot the system from the second memory, and subsequently booting the system from the second memory.

Abstract translation: 提供一种用于执行存储在其中的引导代码的存储器系统和相应的方法，所述存储器系统包括模式解码器，与模式解码器进行信号通信的第一存储器，与模式解码器进行信号通信的第二存储器，以及模式发生器 与模式解码器进行信号通信，用于产生指示将第一和第二存储器中的一个选择为起始存储器的信号; 以及用于执行引导代码的方法，包括最初从第一存储器引导系统，编程用于随后引导的第二存储器，编程模式生成器以随后从第二存储器引导系统，以及随后从第二存储器引导系统。

公开(公告)号：US20080192560A1

公开(公告)日：2008-08-14

申请号：US11734082

申请日：2007-04-11

Applicant: Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

Inventor： Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

IPC: G11C8/12

CPC classification number: G11C11/412 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002

Abstract: An integrated circuit memory system includes an integrated circuit device having a random access memory array, a non-volatile memory array (e.g., flash memory array) and a data transfer circuit therein. The memory arrays and data transfer circuit may be included in a common integrated circuit chip. The random access memory (RAM) array includes a plurality of columns of RAM cells and a first plurality of bit lines, which are electrically connected to the plurality of columns of RAM cells. The non-volatile memory array includes a plurality of columns of non-volatile memory cells and a second plurality of bit lines, which are electrically connected to a plurality of columns of non-volatile memory cells. The data transfer circuit is electrically connected to the first and second pluralities of bit lines. The data transfer circuit is configured to support direct bidirectional communication between the first and second pluralities of bit lines.

Abstract translation: 集成电路存储器系统包括具有随机存取存储器阵列，非易失性存储器阵列（例如闪存阵列）和其中的数据传输电路的集成电路器件。 存储器阵列和数据传输电路可以包括在公共集成电路芯片中。 随机存取存储器（RAM）阵列包括多个RAM单元列和第一多个位线，它们电连接到多个RAM单元列。 非易失性存储器阵列包括多列非易失性存储器单元和第二多个位线，其电连接到多列非易失性存储器单元。 数据传输电路电连接到第一和第二多个位线。 数据传输电路被配置为支持第一和第二多个位线之间的直接双向通信。

公开(公告)号：US20080192542A1

公开(公告)日：2008-08-14

申请号：US11764613

申请日：2007-06-18

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C11/409

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US20080189474A1

公开(公告)日：2008-08-07

申请号：US11761620

申请日：2007-06-12

Applicant: Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G06F12/00

CPC classification number: G11C16/20

Abstract: A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.

Abstract translation: 存储卡包括：响应于外部输入的所有命令的第一存储器芯片; 以及响应命令的第二存储器芯片，在外部输入的命令中与数据的读取，编程和擦除操作相关。 存储在第一存储器芯片中的卡识别信息包括对应于第一和第二存储器芯片的尺寸之和的容量信息。 存储卡的多个存储芯片可用于以各种形式设计具有存储容量的存储卡。

公开(公告)号：US20080144392A1

公开(公告)日：2008-06-19

申请号：US11691703

申请日：2007-03-27

Applicant: Sun-Kwon Kim ,  Byeong-Hoon Lee

Inventor： Sun-Kwon Kim ,  Byeong-Hoon Lee

IPC: G11C11/406

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A method of operating a non-volatile memory device includes maintaining a write voltage at a predetermined voltage level for programming and/or erasing a memory cell of the non-volatile memory device during a time between execution of consecutive write operations. For example, the write voltage may be activated at the predetermined voltage level responsive to an initial write command, and discharge of the write voltage may be prevented responsive to a signal indicating consecutive write commands. Related devices are also discussed.

Abstract translation: 一种操作非易失性存储器件的方法包括将写入电压保持在预定电压电平，以便在执行连续写入操作之间的时间期间编程和/或擦除非易失性存储器件的存储器单元。 例如，可以响应于初始写入命令​​在预定电压电平下激活写入电压，并且可以根据指示连续写入命令的信号来防止写入电压的放电。 还讨论了相关设备。

公开(公告)号：US07379332B2

公开(公告)日：2008-05-27

申请号：US11459547

申请日：2006-07-24

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C11/34

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储器单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US07298190B2

公开(公告)日：2007-11-20

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US20060250844A1

公开(公告)日：2006-11-09

申请号：US11459547

申请日：2006-07-24

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C16/04

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。