公开(公告)号：US20160141013A1

公开(公告)日：2016-05-19

申请号：US14672787

申请日：2015-03-30

申请人： Cavium, Inc.

发明人： David Lin ,  Edward Wade Thoenes

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line.

摘要翻译： 一种用于控制存储器的设备包括存储器控制器，以及与数据线接口并与数据线进行数据通信的数据接口，每个数据线都具有固有的偏斜。 每条数据线都带有数据信号。 数据线将存储器控制器连接到存储器。 该装置还包括每个与对应的数据线相关联的数据去串列，与选通线接口的选通接口，该选通线将存储器控制器连接到存储器，并将定时信号施加到选通线， 串连接到选通线。 每个数据去串串都以读或写模式工作。 特定数据线的数据去串行器对由该线路承载的数据信号施加补偿偏移。

公开(公告)号：US20160140065A1

公开(公告)日：2016-05-19

申请号：US14540414

申请日：2014-11-13

申请人： Cavium, Inc.

发明人： Robert A. Sanzone ,  Wilson P. Snyder, II ,  Richard E. Kessler

IPC分类号： G06F13/364 ,  G06F13/37 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/37 ,  G06F13/4282

摘要： A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.

摘要翻译： 电路管理和控制对诸如多个设备之间的控制和状态寄存器（CSR）的寄存器的访问请求。 特别地，电路选择性地转发或暂停片外访问请求，并转发独立于片外请求状态的片上访问请求。 电路在多个总线上接收访问请求，其中一个或多个可以专用于专用片上请求和/或专用片外请求。 基于先前的片外访问请求的完成状态，选择性地转发或暂停进一步的片外访问请求，而独立于片外请求状态发送片上访问请求。

公开(公告)号：US20160140042A1

公开(公告)日：2016-05-19

申请号：US14541826

申请日：2014-11-14

申请人： Cavium, Inc.

发明人： Shubhendu Sekhar Mukherjee

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F12/0891 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/683

摘要： Managing an instruction cache of a processing element, the instruction cache including a plurality of instruction cache entries, each entry including a mapping of a virtual memory address to one or more processor instructions, includes: issuing, at the processing element, a translation lookaside buffer invalidation instruction for invalidating a translation lookaside buffer entry in a translation lookaside buffer, the translation lookaside buffer entry including a mapping from a range of virtual memory addresses to a range of physical memory addresses; causing invalidation of one or more of the instruction cache entries of the plurality of instruction cache entries in response to the translation lookaside buffer invalidation instruction.

摘要翻译： 管理处理元件的指令高速缓存，所述指令高速缓存包括多个指令高速缓存条目，每个条目包括虚拟存储器地址与一个或多个处理器指令的映射，包括：在处理元件处发出转换后备缓冲器 无效化指令，用于使翻译后备缓冲器中的翻译后备缓冲器条目无效，所述翻译后备缓冲器条目包括从虚拟存储器地址范围到物理存储器地址范围的映射; 导致多个指令高速缓存条目中的一个或多个指令高速缓存条目响应于转换后备缓冲器无效指令而导致无效。

公开(公告)号：US09336328B2

公开(公告)日：2016-05-10

申请号：US14337759

申请日：2014-07-22

申请人： Cavium, Inc.

发明人： Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

IPC分类号： G06F17/00 ,  G06F17/30

CPC分类号： G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

摘要： An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

公开(公告)号：US20160071016A1

公开(公告)日：2016-03-10

申请号：US14922449

申请日：2015-10-26

申请人： Cavium, Inc.

发明人： Rajan Goyal ,  Kenneth A. Bullis

IPC分类号： G06N5/04 ,  G06F17/30

CPC分类号： G06N5/045 ,  G06F16/2246 ,  G06N5/02

摘要： A root node of a decision tree data structure may cover all values of a search space used for packet classification. The search space may include a plurality of rules, the plurality of rules having at least one field. The decision tree data structure may include a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. Scope in the decision tree data structure may be based on comparing a portion of the search space covered by a node to a portion of the search space covered by the node's rules. Scope in the decision tree data structure may be used to identify whether or not a compilation operation may be unproductive. By identifying an unproductive compilation operation it may be avoided, thereby improving compiler efficiency as the unproductive compilation operation may be time-consuming.

摘要翻译： 决策树数据结构的根节点可以覆盖用于分组分类的搜索空间的所有值。 搜索空间可以包括多个规则，该多个规则具有至少一个字段。 所述决策树数据结构可以包括多个节点，所述多个节点包括所述多个规则的子集。 决策树数据结构中的范围可以基于将节点覆盖的搜索空间的一部分与节点规则覆盖的搜索空间的一部分进行比较。 决策树数据结构中的范围可用于识别编译操作是否无效。 通过识别非生产性编译操作，可以避免这种情况，从而提高编译器的效率，因为非生产性编译操作可能是耗时的。

公开(公告)号：US09268694B2

公开(公告)日：2016-02-23

申请号：US14038225

申请日：2013-09-26

申请人： Cavium, Inc.

发明人： Wilson P. Snyder, II ,  Bryan W. Chin ,  Shubhendu S. Mukherjee ,  Michael Bertone ,  Richard E. Kessler

IPC分类号： G06F13/12 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0808 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F2212/151 ,  G06F2212/681

摘要： A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.

摘要翻译： 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 此外，折叠TLB是从MTLB导出的附加高速缓存存储折叠的折叠。 MTLB中的条目，折叠的TLB和其他高速缓存可以保持一致。

公开(公告)号：US09239753B2

公开(公告)日：2016-01-19

申请号：US14629770

申请日：2015-02-24

申请人： Cavium, Inc.

发明人： Aseem Maheshwari ,  Michael S. Bertone ,  Richard E. Kessler

IPC分类号： G11C29/00 ,  G06F11/00 ,  G06F11/10 ,  H03M13/09

CPC分类号： G06F11/1004 ,  G06F11/1016 ,  G06F11/1076 ,  H03M13/09

摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

公开(公告)号：US20150363200A1

公开(公告)日：2015-12-17

申请号：US14828884

申请日：2015-08-18

申请人： Cavium, Inc.

发明人： Najeeb I. Ansari ,  Michael Carns ,  Jeffrey Schroeder ,  Bryan Chin

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30 ,  G06F9/30145 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/50 ,  G06F9/5044 ,  G06F13/362

摘要： In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask. The processor includes an arbitration unit that determines instruction priority among each instruction, assigns an instruction for each available core, and signals the instruction store.

摘要翻译： 在一个实施例中，处理器包括多个处理核心和多个指令存储器，每个指令存储器存储至少一个指令，每个指令具有对应的组号，每个指令存储器具有唯一的标识符。 处理器还包括具有多个组执行掩码的组执行矩阵和包括多个存储执行掩码的存储执行矩阵。 处理器还包括核心选择单元，对于每个指令存储器中的每个指令，从存储执行矩阵中选择存储执行掩码。 每个指令存储器中的每个指令的核心选择单元从组执行矩阵中选择至少一个组执行掩码。 核心选择单元执行逻辑操作以创建核心请求掩码。 处理器包括确定每个指令之间的指令优先级的仲裁单元，为每个可用的核心分配指令，并向指令存储器发出信号。

公开(公告)号：US20150358313A1

公开(公告)日：2015-12-10

申请号：US14829233

申请日：2015-08-18

申请人： CAVIUM, INC.

发明人： Muhammad Raghib HUSSAIN ,  Phanikumar KANCHARLA ,  Ram Kumar MANAPRAGADA

IPC分类号： H04L29/06

CPC分类号： H04L9/3268 ,  G06F9/45558 ,  G06F21/335 ,  G06F21/602 ,  G06F2009/45587 ,  H04L9/321 ,  H04L63/04 ,  H04L63/0485 ,  H04L63/06 ,  H04L63/0823

摘要： A new approach is proposed that contemplates systems and methods to support security communication between a hardware security module (HSM) and a plurality of network-enabled devices to offload their key storage, management, and crypto operations to the HSM. The HSM includes a plurality of HSM service units, each configured to authenticate one of the network-enabled devices based on its credentials and process the key management and crypto operations offloaded from the network-enabled device once it is authenticated. The HSM service unit also communicates results of the key management and crypto operations back to the network-enabled device via the secured communication channel.

摘要翻译： 提出了一种新的方法，其考虑了系统和方法来支持硬件安全模块（HSM）和多个启用网络的设备之间的安全通信，以将其密钥存储，管理和加密操作卸载到HSM。 HSM包括多个HSM服务单元，每个HSM服务单元被配置为基于其凭证来认证网络启用设备中的一个，并且一旦认证就处理从启用网络的设备卸载的密钥管理和密码操作。 HSM服务单元还通过安全通信信道将密钥管理和密码操作的结果传送回启用网络的设备。

公开(公告)号：US09208103B2

公开(公告)日：2015-12-08

申请号：US14038383

申请日：2013-09-26

申请人： Cavium, Inc.

发明人： Richard E. Kessler ,  Bryan W. Chin ,  Michael Bertone

IPC分类号： G06F13/12 ,  G06F12/10 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/1045 ,  G06F12/00 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0888 ,  G06F12/1027 ,  G06F12/1036

摘要： A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.

摘要翻译： 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 可以基于控制配置和接收到的地址的属性来选择性地旁路对MTLB的高速缓存的查找。