公开(公告)号：US20100271317A1

公开(公告)日：2010-10-28

申请号：US12541988

申请日：2009-08-17

Applicant: Ming-Ta Hsieh ,  Chien-Ming Lin ,  Chih-Chung Chen ,  Hsueh-Fang Yin ,  Chia-Lin Liu

Inventor： Ming-Ta Hsieh ,  Chien-Ming Lin ,  Chih-Chung Chen ,  Hsueh-Fang Yin ,  Chia-Lin Liu

IPC: G06F3/041

CPC classification number: G06F3/04883

Abstract: A method of positioning a coordinate suitable for a touch panel includes following steps. When a touch event occurs, the touch panel generates a corresponding detection coordinate periodically until the touch event ends. When the touch event occurs, the detection coordinate generated by the touch panel is sequentially stored. The touch event is ignored until the number of coordinates generated by the touch panel is greater than or equal to N, and N is a positive integer. When the number of coordinates generated by the touch panel is greater than or equal to N, a touch coordinate corresponding to the touch event is generated according to the last generated N detection coordinates. The above-mentioned step of generating the touch coordinate is repeated according to a cycle of generating the detection coordinate by the touch panel so as to renew the touch coordinate until the touch event ends.

Abstract translation: 定位适合于触摸面板的坐标的方法包括以下步骤。 当触摸事件发生时，触摸面板周期性地产生相应的检测坐标，直到触摸事件结束。 当触摸事件发生时，依次存储由触摸面板生成的检测坐标。 触摸事件被忽略，直到触摸面板产生的坐标数大于或等于N，N为正整数。 当触摸面板生成的坐标数大于或等于N时，根据最后生成的N个检测坐标产生与触摸事件相对应的触摸坐标。 根据通过触摸面板生成检测坐标的循环来重复上述产生触摸坐标的步骤，以便更新触摸坐标直到触摸事件结束。

公开(公告)号：US07820457B2

公开(公告)日：2010-10-26

申请号：US11556489

申请日：2006-11-03

Applicant: Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

IPC: G01R31/26

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract translation: 一种方法包括测量多个晶体管的栅极漏电流。 单个应力偏置电压被施加到多个晶体管。 应力偏置电压在相应的应力周期t内导致每个晶体管的驱动电流10％的劣化。 在测量的栅极漏电流和分别由多个晶体管的栅极电压，栅极长度，栅极温度和栅极宽度的组中的一个或多个之间确定一个或多个关系。 基于所测量的栅极泄漏电流和一个或多个关系，估计多个晶体管的负偏置温度不稳定性（NBTI）寿命τ。

公开(公告)号：US20100171725A1

公开(公告)日：2010-07-08

申请号：US12509499

申请日：2009-07-27

Applicant: Chi-Chung Tsai ,  Wen-Chih Tai ,  Chia-Lin Liu ,  Chi-Neng Mo

Inventor： Chi-Chung Tsai ,  Wen-Chih Tai ,  Chia-Lin Liu ,  Chi-Neng Mo

IPC: G09G5/00 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0205 ,  G09G2310/0267 ,  G09G2310/08 ,  G09G2320/0209

Abstract: A method of driving scan lines of a flat panel display uses a gate clock signal, a gate start signal, and an output enabling signal to generate gate signals turning on two scan lines at the same time. The gate clock signal has a first group of clocks and a second group of clocks. The gate start signal has two pulses. The plurality of gate signals for controlling a plurality of scan lines are generated in sequence according to the gate clock signal and the gate start signal, and each gate signal has two pulses. The pulse of each gate signal in the first group of clocks is disabled and the pulse of each gate signal in the second group of clocks is outputted according to the output enabling signal. Thus, the plurality of gate signals can turn on two scan lines at the same time.

Abstract translation: 驱动平板显示器的扫描线的方法使用栅极时钟信号，栅极起始信号和输出使能信号来产生同时开启两条扫描线的栅极信号。 门时钟信号具有第一组时钟和第二组时钟。 门起始信号有两个脉冲。 根据栅极时钟信号和栅极起始信号依次产生用于控制多个扫描线的多个栅极信号，并且每个栅极信号具有两个脉冲。 第一组时钟中的每个门信号的脉冲被禁用，并且根据输出使能信号输出第二组时钟中的每个门信号的脉冲。 因此，多个门信号可以同时打开两条扫描线。

公开(公告)号：US07696578B2

公开(公告)日：2010-04-13

申请号：US11349804

申请日：2006-02-08

Applicant: Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

Inventor： Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract translation: 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。

公开(公告)号：US20100062410A1

公开(公告)日：2010-03-11

申请号：US12556735

申请日：2009-09-10

Applicant: Cheng-Hui CHIANG ,  Chia-Lin Lu ,  Tzu-Yin Lu ,  Pei-Ching Cheng ,  Kuei-Yin Lin ,  Meng-Chieh Wu ,  Shu-Ching Wang ,  Yu-Cheng Hsiao

Inventor： Cheng-Hui CHIANG ,  Chia-Lin Lu ,  Tzu-Yin Lu ,  Pei-Ching Cheng ,  Kuei-Yin Lin ,  Meng-Chieh Wu ,  Shu-Ching Wang ,  Yu-Cheng Hsiao

IPC: G09B7/00

CPC classification number: G09B7/00

Abstract: The computerized testing device with a network editing interface in accordance with the present invention allows a teacher to generate customized quizzes or teaching materials for students logging into the computerized testing device to take tests through a network. The computerized testing device comprises an examination managing module, a content database, a testing module and a recording module. The network editing interface allows teachers to generate quizzes or teaching materials, and comprises a quiz database, a template database, a teacher database and a network editing interface.

Abstract translation: 具有根据本发明的网络编辑界面的计算机化测试设备允许教师为登录到计算机化测试设备的学生生成定制的测验或教学材料以通过网络进行测试。 计算机化测试装置包括检查管理模块，内容数据库，测试模块和记录模块。 网络编辑界面允许教师生成测验或教学材料，包括测验数据库，模板数据库，教师数据库和网络编辑界面。

公开(公告)号：US20100051965A1

公开(公告)日：2010-03-04

申请号：US12509339

申请日：2009-07-24

Applicant: Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou ,  Hung-Ta Lin

Inventor： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou ,  Hung-Ta Lin

IPC: H01L33/00

CPC classification number: H01L33/007 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/223 ,  H01L21/26506 ,  H01L33/025

Abstract: A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixing with atoms of the substrate. In this manner, a crystalline structure is maintained upon which the LED structure may be formed.

Abstract translation: 提供了一种发光二极管（LED）装置。 LED装置形成在具有含碳层的基板上。 将碳原子引入衬底中以防止或减少来自上层金属/金属合金过渡层的原子与衬底的原子的混合。 以这种方式，保持可以形成LED结构的晶体结构。

公开(公告)号：US20100032718A1

公开(公告)日：2010-02-11

申请号：US12189562

申请日：2008-08-11

Applicant: Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

Inventor： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC: H01L33/00 ,  H01L29/20

CPC classification number: H01L33/04 ,  H01L33/12 ,  H01L33/32

Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

Abstract translation: 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

公开(公告)号：US20100026482A1

公开(公告)日：2010-02-04

申请号：US11827591

申请日：2007-07-12

Applicant: Alexander Grichener ,  Chuang-Chia Lin

Inventor： Alexander Grichener ,  Chuang-Chia Lin

IPC: G08B1/08 ,  E05C19/10

CPC classification number: E05B39/04 ,  B64D29/06 ,  E05C19/145 ,  Y10T292/0948

Abstract: The invention provides a sensor for determining when a latch for securing an engine cowl on an aircraft is secured by detecting the proximity of a latch hook and a latch pin. The sensor includes a resonant circuit configured and adapted to transmit a status signal when the latch is in a secured state. The sensor also includes a means for conveying status information of the latch to a location remote from the latch based on the status signal, the conveying means being operably connected to the resonant circuit. The invention also provides a method of determining when a latch is open or secured by detecting the proximity of a latch hook and a latch pin.

Abstract translation: 本发明提供了一种传感器，用于通过检测闩锁钩和闩锁销的接近来确定何时用于固定飞机上的发动机罩的闩锁。 所述传感器包括谐振电路，所述谐振电路经配置并适于在所述闩锁处于安全状态时发送状态信号。 传感器还包括用于基于状态信号将闩锁的状态信息传送到远离闩锁的位置的装置，该传送装置可操作地连接到谐振电路。 本发明还提供了一种通过检测闩锁钩和闩锁销的接近来确定闩锁何时打开或固定的方法。

公开(公告)号：US20100015787A1

公开(公告)日：2010-01-21

申请号：US12191013

申请日：2008-08-13

Applicant: Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

Inventor： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

IPC: H01L21/205

CPC classification number: H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02617 ,  H01L21/02664

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.

Abstract translation: 形成半导体结构的方法包括提供基板; 在衬底上形成缓冲/成核层; 在缓冲/成核层上形成III族氮化物（III族氮化物）层; 并对该III族氮化物层进行氮化。 形成III族氮化物层的步骤包括金属有机化学气相沉积。

公开(公告)号：US07650598B2

公开(公告)日：2010-01-19

申请号：US11463538

申请日：2006-08-09

Applicant: Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

Inventor： Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

IPC: G06F12/00

CPC classification number: G06F8/441

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract translation: 一种为PAC处理器分配寄存器的方法。 PAC处理器具有第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行本发明的功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用 PAC处理器。