公开(公告)号：US20140266114A1

公开(公告)日：2014-09-18

申请号：US14291426

申请日：2014-05-30

Applicant: Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

Inventor： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

Abstract translation: 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

公开(公告)号：US08673312B2

公开(公告)日：2014-03-18

申请号：US13560593

申请日：2012-07-27

Applicant: Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

Inventor： Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

IPC: A61K39/38 ,  A61K35/00 ,  A61K48/00 ,  C12P9/00 ,  C07C7/12

CPC classification number: C07K14/205

Abstract: Helicobacter pylori is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. Helicobacter pylori neutrophil-activating protein (HP-NAP), a virulence factor of Helicobacter pylori, plays an important role in pathogenesis of Helicobacter pylori infection. Since HP-NAP has been proposed as a candidate vaccine against Helicobacter pylori infection, an efficient way to obtain pure HP-NAP needs to be developed. In the present invention, recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli was purified through a single step of DEAE SEPHADEX ion-exchange chromatography with high purity. Also, purified recombinant HP-NAP was able to stimulate neutrophils to produce reactive oxygen species. Thus, recombinant HP-NAP obtained from our Bacillus subtilis expression system and Escherichia coli expression system is functionally active. Furthermore, this one-step negative purification method should provide an efficient way to purify recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli for basic studies, vaccine development, or drug design.

Abstract translation: 幽门螺杆菌与慢性胃炎，消化性溃疡病和胃腺癌密切相关。 幽门螺杆菌嗜中性粒细胞激活蛋白（HP-NAP）是幽门螺杆菌的毒力因子，在幽门螺杆菌感染的发病机制中起重要作用。 由于HP-NAP已被提出作为针对幽门螺杆菌感染的候选疫苗，因此需要开发获得纯HP-NAP的有效途径。 在本发明中，通过具有高纯度的DEAE SEPHADEX离子交换色谱法的一步纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP。 此外，纯化的重组HP-NAP能够刺激嗜中性粒细胞产生活性氧。 因此，从我们的枯草芽孢杆菌表达系统和大肠杆菌表达系统获得的重组HP-NAP在功能上是活性的。 此外，该一步负纯化方法应提供一种有效的方法来纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP用于基础研究，疫苗开发或药物设计。

公开(公告)号：US20140015582A1

公开(公告)日：2014-01-16

申请号：US13547396

申请日：2012-07-12

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

IPC: H03K3/356

CPC classification number: H03K5/08 ,  H03K3/356139 ,  H04L27/01

Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

Abstract translation: 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

公开(公告)号：US20130346811A1

公开(公告)日：2013-12-26

申请号：US13528877

申请日：2012-06-21

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

IPC: G06F1/04 ,  G06F11/00

CPC classification number: H04L25/03057 ,  H04L25/06 ,  H04L25/08

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract translation: 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US20130141170A1

公开(公告)日：2013-06-06

申请号：US13312228

申请日：2011-12-06

Applicant: Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H03F3/68

CPC classification number: H03F3/68 ,  H03F1/42 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2200/405 ,  H03F2203/45638 ,  H03F2203/45702

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract translation: 共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。 通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。 具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

公开(公告)号：US08456942B2

公开(公告)日：2013-06-04

申请号：US13535034

申请日：2012-06-27

Applicant: Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

Inventor： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C11/4074

Abstract: A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.

Abstract translation: 提供了一种用于调节电荷泵的调节器。 调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。 第一电压与电荷泵的输出电压相关联。 第二电压与内部电源电压和参考电压Vref相关联。

公开(公告)号：US08378756B2

公开(公告)日：2013-02-19

申请号：US12782064

申请日：2010-05-18

Applicant: Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03B5/30 ,  G01C19/00

CPC classification number: H03B5/30

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract translation: 一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

公开(公告)号：US08354862B2

公开(公告)日：2013-01-15

申请号：US13448878

申请日：2012-04-17

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract translation: 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。

公开(公告)号：US20120223752A1

公开(公告)日：2012-09-06

申请号：US13039095

申请日：2011-03-02

Applicant: Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

Inventor： Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

IPC: H03L7/06

CPC classification number: H03L7/0896 ,  H03L7/089 ,  H03L7/0893

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

Abstract translation: 锁相环（PLL）包括配置成提供输出信号的压控振荡器（VCO）。 相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。 第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。 第二电荷泵被配置为接收第一控制信号并提供第二电压信号。 比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。

公开(公告)号：US20120200323A1

公开(公告)日：2012-08-09

申请号：US13448878

申请日：2012-04-17

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract translation: 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。