公开(公告)号：US20050219970A1

公开(公告)日：2005-10-06

申请号：US11160114

申请日：2005-06-09

Applicant: Tzu-Ming Chou ,  Kun-Hung Hsieh ,  Wei-Yu Lin ,  Yao-Lung Chuang ,  Chun-Jen Chen ,  Kuo-Jung Lan

Inventor： Tzu-Ming Chou ,  Kun-Hung Hsieh ,  Wei-Yu Lin ,  Yao-Lung Chuang ,  Chun-Jen Chen ,  Kuo-Jung Lan

IPC: G11B5/09 ,  G11B7/00 ,  G11B7/0045 ,  G11B7/005 ,  G11B7/085 ,  G11B7/09 ,  G11B19/04 ,  G11B19/26 ,  G11B27/13

CPC classification number: G11B19/041 ,  G11B7/0045 ,  G11B7/1267 ,  G11B19/04 ,  G11B19/26 ,  G11B19/28

Abstract: A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal, the frequency of buffer under-run occurrence, the temperature of the drive, the wobble jitter and the level of write power is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. If at least one of the temperature of the drive, the wobble jitter and the estimated write power exceeds the reset value before recording starts, the rotation speed of the optical disk drive is decreased before recording.

Abstract translation: 光盘驱动器的记录方法如下进行。 首先，聚焦误差信号的电平，跟踪误差信号的电平，摆动同步模式损耗，解调摆动信号的误码率，缓冲器欠载发生的频率， 驱动，检测摆动抖动和写入电平。 如果至少一个检测值超过预设值，则停止录制。 然后，光盘驱动器的旋转速度降低，并且以降低的转速恢复记录。 如果在记录开始之前驱动器的温度，摆动抖动和估计的写入功率中的至少一个超过复位值，则在记录之前光盘驱动器的转速减小。

公开(公告)号：US20050125763A1

公开(公告)日：2005-06-09

申请号：US10880903

申请日：2004-06-30

Applicant: Ko-Feng Lin ,  Yi-Hsu Chen ,  Lee-Chih Yeh ,  Chun-Jen Chen ,  Ta-Chin Chin

Inventor： Ko-Feng Lin ,  Yi-Hsu Chen ,  Lee-Chih Yeh ,  Chun-Jen Chen ,  Ta-Chin Chin

IPC: G06F13/10 ,  G06F17/50 ,  G03F9/00 ,  G21K5/00

CPC classification number: G06F17/5068

Abstract: Provided are a system and method for creating a reticle field layout (RFL). In one example, the method includes receiving information for a RFL design by a computer system directly from a user via a computer interface. The RFL design is automatically verified using predefined specification and design rules accessible to the computer system. The RFL design may be modified by adding additional features before being finalized.

Abstract translation: 提供了一种用于创建掩模版场布局（RFL）的系统和方法。 在一个示例中，该方法包括通过计算机系统直接从用户经由计算机接口接收RFL设计的信息。 使用计算机系统可访问的预定义​​规范和设计规则自动验证RFL设计。 RFL设计可以通过在定稿之前添加附加功能来修改。

公开(公告)号：US20050000807A1

公开(公告)日：2005-01-06

申请号：US10722549

申请日：2003-11-28

Applicant: Kuo-Jeng Wang ,  Chun-Jen Chen

Inventor： Kuo-Jeng Wang ,  Chun-Jen Chen

IPC: C12M1/00 ,  C12M1/40 ,  C12N9/00 ,  G01N33/48 ,  G01N33/487

CPC classification number: G01N33/48785

Abstract: A biosensor with multi-channel A/D conversion and a method thereof are provided. The present biosensor includes a chip generating a time-dependent analog signal in response to a content of a specific component of a specimen provided thereon, a multi-channel A/D converter, and a microprocessor. The multi-channel A/D converter has multiple channels simultaneously receiving the time-dependent analog signal in each sampling interval to convert the time-dependent analog signal to a set of digital signals. The microprocessor receives the sets of digital signals in a period of sampling time and determines the content of the specific component based on the sets of digital signals. The present biosensor provides a multi-channel A/D conversion for the time-dependent analog signal to improve the resolution of the determination of the content of the specific component.

Abstract translation: 提供了具有多通道A / D转换的生物传感器及其方法。 本生物传感器包括响应于其上提供的试样的特定部件的内容，多通道A / D转换器和微处理器产生时间相关模拟信号的芯片。 多通道A / D转换器具有多个通道，每个采样间隔同时接收时间相关的模拟信号，以将时间相关的模拟信号转换成一组数字信号。 微处理器在采样时间段内接收数字信号组，并根据数字信号组确定特定分量的内容。 本生物传感器为时间依赖模拟信号提供多通道A / D转换，以提高确定特定部件内容的分辨率。

公开(公告)号：US06711010B2

公开(公告)日：2004-03-23

申请号：US10095942

申请日：2002-03-13

Applicant: Ti-Li Wei ,  Chun-Jung Tsai ,  Chun-Jen Chen

Inventor： Ti-Li Wei ,  Chun-Jung Tsai ,  Chun-Jen Chen

IPC: G06F116

CPC classification number: G06K13/0825 ,  G06K13/08 ,  G06K13/0806

Abstract: A memory card ejecting structure includes an electrically insulative frame base, the frame base having a receiving unit mounted with a set of terminals for receiving a memory card and two arms forwardly extended from two opposite lateral sides of the receiving unit, the receiving unit having an endless guide groove, an ejecting member slidably mounted in the frame base and adapted for ejecting the inserted memory card out of the receiving unit, and a spring member connected between the ejecting member and one arm of the frame base, the spring member having an angled locating wire rod backwardly extended from a rear end ring thereof and positioned in the endless guide groove to hold the spring member between a stretched position and a released position.

Abstract translation: 存储卡弹出结构包括电绝缘框架基座，所述框架基座具有安装有用于接收存储卡的一组端子的接收单元和从所述接收单元的两个相对侧向前延伸的两个臂，所述接收单元具有 环形引导槽，可滑动地安装在框架基座中并适于将插入的存储卡从接收单元中排出的弹出构件以及连接在排出构件和框架基座的一个臂之间的弹簧构件，弹簧构件具有成角度 将线材从其后端环向后延伸并定位在环形引导槽中，以将弹簧构件保持在拉伸位置和释放位置之间。

公开(公告)号：US20130007690A1

公开(公告)日：2013-01-03

申请号：US13441849

申请日：2012-04-07

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  SHIN-TING YEN

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU ,  SHIN-TING YEN

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.

Abstract translation: 电子设备读取要从存储装置制造的印刷电路板（PCB）的布局文件，获得在一个或多个层中的每一个中的电源区域和地面迹线区域上分布的铜包层的长度信息和截面面积信息 通过分析布局文件来制造PCB，并且根据长度信息，截面面积信息，铜包层的电阻值和电源模块的预设参数来计算一个或多个层中的每一个中的功率损耗 以及位于PCB上的集成电路（IC）负载。 响应于层中的功率损耗超过预设范围的确定，电子设备指示需要重新设计的PCB布局文件中的层的电源区域和地面迹线区域的位置。

公开(公告)号：US08336020B2

公开(公告)日：2012-12-18

申请号：US13213072

申请日：2011-08-18

Applicant: Dan-Chen Wu ,  Shou-Kuo Hsu ,  Cheng-Hsien Lee ,  Chun-Jen Chen

Inventor： Dan-Chen Wu ,  Shou-Kuo Hsu ,  Cheng-Hsien Lee ,  Chun-Jen Chen

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.

Abstract translation: 在用于检查印刷电路板（PCB）的布局的方法中，从PCB的电子布局图确定要检查的部件，并且可以选择可用于该部件的输电线。 检查布局图以确定组件是否连接到电力传输线，并进一步检查以确定组件的多个接地引脚是否连接到电力传输线。 如果多个接地引脚连接到电力传输线，则确定由组件的两个或更多个接地引脚共享的通孔。 共享通孔在布局图上标出。

公开(公告)号：US20120292090A1

公开(公告)日：2012-11-22

申请号：US13166790

申请日：2011-06-22

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/11 ,  H05K2201/09663 ,  H05K2201/09845

Abstract: A printed circuit board (PCB) comprising a first circuit area, a second circuit area, a plurality of connecting elements, and a plurality of connecting terminals placed on the first circuit area, wherein the first circuit area are electrically connected to the second circuit area through the plurality of connecting elements, the plurality of connecting elements are arranged in sequence to extend toward the plurality of connecting terminals, to form shortest current paths from the second circuit area via corresponding one of the connecting elements to the connecting terminals, respectively, and each shortest current path between the corresponding one of the connecting elements and the corresponding one of the connecting terminals is uncoated with conductive material.

Abstract translation: 一种印刷电路板（PCB），包括第一电路区域，第二电路区域，多个连接元件和放置在第一电路区域上的多个连接端子，其中第一电路区域电连接到第二电路区域 通过多个连接元件，多个连接元件依次布置成朝向多个连接端子延伸，以形成从第二电路区域经由对应的一个连接元件到连接端子的最短电流路径，以及 连接元件与对应的一个连接端子之间的每个最短电流路径都不用导电材料涂覆。

公开(公告)号：US08261230B2

公开(公告)日：2012-09-04

申请号：US12774685

申请日：2010-05-05

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

IPC: G06F17/50 ,  G06F9/455 ,  G05D17/00

CPC classification number: G06F17/5063

Abstract: A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.

Abstract translation: 用于优化电流过载保护电路的系统包括输入装置，数据存储装置，中央处理装置和显示器。 中央处理装置包括存储模块，控制模块和计算模块。 存储模块在其中存储VI应用。 控制模块从输入设备接收指令，并从数据存储设备中选择电流过载保护电路的虚拟电子部件，并选择电子部件的连接。 电流过载保护电路在VI应用中完成并运行; 显着影响最大保护电流的电子元件被标记。 计算模块基于标记的电子元件计算电流过载保护电路的正态分布样本。 显示屏显示电流过载保护电路是否符合过程能力标准。

公开(公告)号：US08237499B2

公开(公告)日：2012-08-07

申请号：US12775486

申请日：2010-05-07

Applicant: Chun-Jen Chen ,  Chih-Chang Lee

Inventor： Chun-Jen Chen ,  Chih-Chang Lee

IPC: H03G3/20

CPC classification number: H03F3/24 ,  H03F1/0266 ,  H03F3/195 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/555

Abstract: The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.

Abstract translation: 本公开示出了前馈控制包络调制器及其前馈控制电路。 前馈控制包络调制器包括线性放大器电路，开关放大器和前馈控制电路。 线性放大器电路放大输入电压信号，以将输出电压信号输出到负载节点。 开关放大器接收比较信号，并根据比较信号将负载节点输出开关电流。 前馈控制电路包括一个重复的线性放大器电路和一个滞后比较器。 重复的线性放大器电路放大输入电压信号，以便输出参考电压信号，其中重复线性放大器电路的放大增益与线性放大器电路的放大增益相同。 迟滞比较器比较输出电压信号和参考电压信号，以输出比较信号。

公开(公告)号：US20120090884A1

公开(公告)日：2012-04-19

申请号：US12981460

申请日：2010-12-29

Applicant: TSUNG-SHENG HUANG ,  YING-TSO LAI ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  YING-TSO LAI ,  CHUN-JEN CHEN ,  WEI-CHIEH CHOU

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/0201 ,  H05K1/116 ,  H05K2201/09309

Abstract: A printed circuit board includes a plurality of power layers. Each power layer defining a number of vias arranged in a number of rows. The number of the power layers is N (N>3). The power layers are defined as a 1st, 2nd, . . . , Nth power layer. The vias of the 1st power layer are connected to other power layers by a step-shaped connection means.

Abstract translation: 印刷电路板包括多个功率层。 每个功率层定义了以多行布置的多个通孔。 功率层的数量为N（N> 3）。 功率层定义为1，2，...。 。 。 ，第N功率层。 第一功率层的通孔通过阶梯形连接装置连接到其它功率层。