公开(公告)号：US11996167B2

公开(公告)日：2024-05-28

申请号：US17636982

申请日：2020-08-14

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Mark Evan Marson ,  Joel Wittenauer

IPC: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/0035

Abstract: A random number generator selects addresses while a ‘scoreboard’ bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an address has already been output, a second address which has not been used yet is output rather than the randomly selected one. The second address may be selected from nearby addresses that have not already been output.

公开(公告)号：US11983280B2

公开(公告)日：2024-05-14

申请号：US17309937

申请日：2020-01-06

Applicant: Cryptography Research, Inc.

Inventor： Michael Alexander Hamburg ,  Michael Tunstall ,  Michael Hutter

IPC: G06F21/00 ,  G06F7/523 ,  G06F7/58 ,  G06F17/16 ,  G06F21/60 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F7/523 ,  G06F7/588 ,  G06F17/16 ,  G06F21/78

Abstract: Aspects of the present disclosure involve a method and a system to support execution of the method to perform a cryptographic operation involving a first vector and a second vector, by projectively scaling the first vector, performing a first operation involving the scaled first vector and the second vector to obtain a third vector, generating a random number, storing the third vector in a first location, responsive to the random number having a first value, or in a second location, responsive to the random number having a second value, and performing a second operation involving a first input and a second input, wherein, based on the random number having the first value or the second value, the first input is the third vector stored in the first location or the second location and the second input is a fourth vector stored in the second location or the first location.

公开(公告)号：US11934323B2

公开(公告)日：2024-03-19

申请号：US17353374

申请日：2021-06-21

Applicant: Cryptography Research, Inc.

Inventor： Ambuj Kumar

IPC: G06F12/14 ,  H04L9/08 ,  H04L9/32 ,  H04L9/40

CPC classification number: G06F12/1408 ,  H04L9/0825 ,  H04L9/0861 ,  H04L9/3242 ,  H04L63/06 ,  G06F2212/1052

Abstract: A symmetric key that is stored at a device may be received. A public key from a remote entity may also be received at the device. Furthermore, a derived key may be generated based on a one way function between the symmetric key that is stored at the device and the public key that is received from the remote entity. The derived key may be encrypted with the public key and transmitted to the remote entity. The encryption of the derived key with the public key may provide secure transmission of the derived key to an authorized remote entity with a private key that may be used to decrypt the encrypted derived key.

公开(公告)号：US20240056295A1

公开(公告)日：2024-02-15

申请号：US18229328

申请日：2023-08-02

Applicant: Cryptography Research, Inc.

Inventor： Mark Evan Marson ,  Thi Nguyen ,  Matthew Evan Orzen

IPC: H04L9/08 ,  G06F8/65

CPC classification number: H04L9/088 ,  G06F8/65

Abstract: Aspects of the present disclosure involve a method, a system and a computer readable memory to perform a secure update of a target device, including communicating an update instruction to the target device, generating one or more data values using the update instruction, generating a first authentication value using the data value(s), receiving a second authentication value from the target device, wherein the second authentication value is generated by the target device in response to the update instruction, and determining whether the secure update has been successful based on a comparison of the first authentication value and the second authentication value.

公开(公告)号：US11861374B2

公开(公告)日：2024-01-02

申请号：US18063984

申请日：2022-12-09

Applicant: Cryptography Research, Inc.

Inventor： Ashish Raj ,  Joel Wittenauer ,  Winthrop John Wu ,  Qinglai Xiao ,  Samatha Gummalla ,  Bryan Jason Wang

IPC: G06F9/445

CPC classification number: G06F9/445

Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

公开(公告)号：US20230396410A1

公开(公告)日：2023-12-07

申请号：US18204694

申请日：2023-06-01

Applicant: CRYPTOGRAPHY RESEARCH, INC.

Inventor： Michael Alexander Hamburg

IPC: H04L9/06

CPC classification number: H04L9/0618

Abstract: Aspects and implementations include systems and techniques for encryption and decryption of error-corrected codewords for combined protection against corruption of data and adversarial attacks, including obtaining a block of data that has a first plurality of symbols, generating, based on the first plurality of symbols, a second plurality of symbols, wherein the second plurality of symbols includes one or more error correction symbols for the first plurality of symbols, encrypting the second plurality of symbols using a set of symbol-level ciphers (SLCs) to obtain an encrypted plurality of symbols, and using the encrypted plurality of symbols in a computer operation.

公开(公告)号：US11797683B2

公开(公告)日：2023-10-24

申请号：US17382333

申请日：2021-07-21

Applicant: Cryptography Research, Inc.

Inventor： Paul C. Kocher ,  Pankaj Rohatgi ,  Joshua M. Jaffe

IPC: G06F21/57 ,  G06F21/60 ,  H04L9/08 ,  H04L9/32 ,  G06F21/55 ,  H04L9/00 ,  G06F12/14 ,  H04L9/06 ,  H04L9/16 ,  G06F9/445 ,  G06F21/76 ,  G06F8/71 ,  H04L9/40 ,  G06F21/75

CPC classification number: G06F21/575 ,  G06F8/71 ,  G06F9/44505 ,  G06F12/1408 ,  G06F21/556 ,  G06F21/602 ,  G06F21/76 ,  H04L9/003 ,  H04L9/0631 ,  H04L9/085 ,  H04L9/088 ,  H04L9/0861 ,  H04L9/0894 ,  H04L9/16 ,  H04L9/3236 ,  H04L9/3247 ,  H04L9/3271 ,  G06F21/755 ,  G06F2212/402 ,  G06F2221/034 ,  G06F2221/2107 ,  G06F2221/2125 ,  G06F2221/2145 ,  H04L9/50 ,  H04L63/0428 ,  H04L63/0869 ,  H04L2209/24 ,  H04L2209/56 ,  H04L2463/061

Abstract: A method for performing a security chip protocol comprises receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware determines a path through a key tree based at least in part on the message. The processing hardware derives a validator at least in part from the secret value using a sequence of entropy redistribution operations associated with the path through the key tree. The processing hardware exchanges the validator between the security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

公开(公告)号：US11765149B2

公开(公告)日：2023-09-19

申请号：US16593377

申请日：2019-10-04

Applicant: Cryptography Research, Inc.

Inventor： Ambuj Kumar ,  Daniel Beitel ,  Benjamin Che-Ming Jun

IPC: H04L9/00 ,  H04L9/40 ,  G06F21/57 ,  H04L9/08 ,  H04L9/32 ,  H04W12/04 ,  H04W12/30 ,  G06F12/14

CPC classification number: H04L63/061 ,  G06F12/1408 ,  G06F21/575 ,  H04L9/0894 ,  H04L9/3236 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0442 ,  H04W12/04 ,  H04W12/35 ,  G06F2212/1052

Abstract: A first instruction to store an entity identification (ID) in a memory of a device may be received. The entity ID may be stored in the memory in response to receiving the first instruction. Furthermore, a second instruction to store a value based on a key in the memory of the device may be received. A determination may be made as to whether the value based on the key that is to be stored in the memory corresponds to the entity ID that is stored in the memory. The value based on the key may be stored in the memory of the device when the value based on the key corresponds to the entity ID.

公开(公告)号：US11743028B2

公开(公告)日：2023-08-29

申请号：US17009361

申请日：2020-09-01

Applicant: Cryptography Research, Inc.

Inventor： Jean-Michel Cioranesco ,  Elena Trichina ,  Elke De Mulder ,  Matthew Pond Baker

IPC: H04L9/00 ,  H04L9/14 ,  H04L9/06

CPC classification number: H04L9/002 ,  H04L9/0618 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/16

Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks. An example apparatus for implementing a block cipher may comprise: a first register configured to store a first pre-computed mask value represented by a combination of a first random value and a second random value; a second register configured to store an output mask value, wherein the output mask value is an inverse permutation function of the first random value; a third register configured to store a second pre-computed mask value represented by a combination the first pre-computed mask value and a permutation function of the output mask value; a fourth register configured to store an input mask value, wherein the input mask value is a combination of an expansion function of the first random value and a key mask value; a non-linear transformation circuit configured to apply the expansion function to a masked round state, perform a non-linear transformation of a combination of a masked key with an output of the expansion function, and apply the permutation function to the output of the non-linear transformation, wherein the non-linear transformation is defined using the input mask value stored in the fourth register and the output mask value stored in the second register; and two round feedback circuits configured to swap the masked round state produced by the non-linear transformation and combine the masked round state with the first pre-computed mask value stored in the first register and the second pre-computed mask value stored in the third register.

公开(公告)号：US11700111B2

公开(公告)日：2023-07-11

申请号：US16909530

申请日：2020-06-23

Applicant: Cryptography Research, Inc.

Inventor： Michael Tunstall

IPC: G06F21/75 ,  H04L9/06 ,  H04L9/00

CPC classification number: H04L9/0625 ,  G06F21/755 ,  H04L9/003 ,  H04L9/0631 ,  H04L2209/043 ,  H04L2209/046 ,  H04L2209/24

Abstract: Systems and methods for protecting block cipher computation operations from external monitoring attacks. An example apparatus for implementing a block cipher may comprise a memory device to store instructions for computing a block cipher; and a processing device coupled to the memory device. The processing device performs a Data Encryption Standard (DES) cryptographic operation with multiple rounds of a Feistel structure, each round including a substitution function and a transformation function that combines an expansion function and a permutation function into a single operation. The transformation function transforms a first input portion of an internal state of the respective round and a second input portion of the internal state into a first output portion and a second output portion of data. The second output portion is equal to the first input portion and the first output portion is dependent on a combined permutation output from the transformation function.